公开(公告)号：US10886405B2

公开(公告)日：2021-01-05

申请号：US15371293

申请日：2016-12-07

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Yung-Hsiang Chen ,  Yao-Wen Chang ,  Chu-Yung Liu ,  I-Chen Yang ,  Hsin-Wen Chang

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L27/112 ,  H01L29/66 ,  H01L29/06

摘要： A semiconductor structure includes a first source/drain region, a second source/drain region, a channel doping region, a gate structure, a first well and a second well. The second source/drain region is disposed opposite to the first source/drain region. The channel doping region is disposed between the first source/drain region and the second source/drain region. The gate structure is disposed on the channel doping region. The first well has a first portion disposed under the first source/drain region. The second well is disposed opposite to the first well and separated from the second source/drain region. The first source/drain region, the second source/drain region and the channel doping region have a first conductive type. The first well and the second well have a second conductive type different from the first conductive type.

公开(公告)号：US09437303B1

公开(公告)日：2016-09-06

申请号：US14834809

申请日：2015-08-25

申请人： MACRONIX International Co., Ltd.

发明人： Chu-Yung Liu ,  Hsing-Wen Chang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3459

摘要： A programming method of a memory array is provided and includes following steps, wherein the memory array includes a target memory cell and two periphery memory cells electrically connected to a first word line. After a first programming operation is performed on the target memory cell, the target memory cell and the two periphery memory cells are verified to obtain a first verification result. Whether to perform a second programming operation or a third programming operation on the target memory cell is determined according to the first verification result. The step of performing the second programming operation or the third programming operation on the target memory cell includes: turning off a first transistor and a second transistor; and increasing a level of a passing voltage for turning on a plurality of non-target memory cells and a level of a programming voltage transmitted by the first word line.

摘要翻译： 提供了存储器阵列的编程方法，并且包括以下步骤，其中存储器阵列包括电连接到第一字线的目标存储器单元和两个外围存储器单元。 在对目标存储单元执行第一编程操作之后，验证目标存储单元和两个周边存储单元以获得第一验证结果。 根据第一验证结果确定是否对目标存储单元执行第二编程操作或第三编程操作。 对目标存储单元执行第二编程操作或第三编程操作的步骤包括：关闭第一晶体管和第二晶体管; 以及增加用于接通多个非目标存储单元的通过电压的电平以及由第一字线发送的编程电压的电平。

公开(公告)号：US20140126296A1

公开(公告)日：2014-05-08

申请号：US14151617

申请日：2014-01-09

申请人： MACRONIX International Co., Ltd.

发明人： Hsing-Wen Chang ,  Yao-Wen Chang ,  Chu-Yung Liu

IPC分类号： G11C16/08

CPC分类号： G11C16/08 ,  G11C16/0483 ,  G11C16/3418

摘要： A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is an integer greater than 2. The memory array includes a plurality of memory cells and is connected to a plurality of word lines and a plurality of bit lines. The row decoder drives a specific word line among the word lines during an enabling period. Each of the page buffers is connected to N bit lines of the bit lines, and N is an integer equal to or greater than 3. A jth page buffer drives an (N*(j−1)+1)th bit line to an (N*j)th bit line during the enabling period, and one of an (i−1)th bit line and an (i+1)th bit line is not driven when an ith bit line is not driven, wherein j is an integer and 1≦j≦M, and i is an integer and 1

摘要翻译： 提供了包括存储器阵列，行解码器和M页缓冲器的闪速存储器件，其中M是大于2的整数。存储器阵列包括多个存储器单元，并且连接到多个字线和多个字线 位线。 行解码器在使能期间驱动字线中的特定字线。 每个页缓冲器连接到位线的N位线，N是等于或大于3的整数。第j页缓冲器驱动（N *（j-1）+1）位线到 （N * j）位线，并且当第i位线未被驱动时，不驱动第（i-1）位线和第（i + 1）位线之一，其中j为 整数和1＆nlE; j＆nlE; M，i是整数，1