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公开(公告)号：US20170010321A1
公开(公告)日：2017-01-12
申请号：US14792148
申请日：2015-07-06
发明人： Shih-Yu Wang , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： G01R31/28
CPC分类号： G01R31/2853 , G01R1/0491 , G01R31/3004
摘要： Latch-up test device and method are provided, and the method includes following steps. A set operation is performed for setting a basic test value according to a test range and setting a trigger pulse and a predetermined error value by the basic test value. A test on a test chip in a wafer under test is performed by the trigger pulse, and whether the test chip is in a latch-up state is determined. Whether to update a test range and a latch-up threshold value and whether to return to the step of performing the set operation are determined according to a determination result, the latch-up threshold value and the basic test value. When the test chip is in the latch-up state and a difference between the latch-up threshold value and the basic test value is not greater than the predetermined error value, the test on the test chip is stopped.
摘要翻译： 提供了锁存测试装置和方法，该方法包括以下步骤。 执行设定操作，根据测试范围设置基本测试值，并通过基本测试值设置触发脉冲和预定误差值。 通过触发脉冲进行被测晶片中的测试芯片的测试，并确定测试芯片是否处于闭锁状态。 根据确定结果，闩锁阈值和基本测试值来确定是否更新测试范围和锁存阈值以及是否返回到执行设置操作的步骤。 当测试芯片处于闩锁状态并且闩锁阈值和基本测试值之间的差异不大于预定误差值时，测试芯片上的测试被停止。
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公开(公告)号：US09437303B1
公开(公告)日：2016-09-06
申请号：US14834809
申请日：2015-08-25
发明人： Chu-Yung Liu , Hsing-Wen Chang , Yao-Wen Chang , Tao-Cheng Lu
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3459
摘要： A programming method of a memory array is provided and includes following steps, wherein the memory array includes a target memory cell and two periphery memory cells electrically connected to a first word line. After a first programming operation is performed on the target memory cell, the target memory cell and the two periphery memory cells are verified to obtain a first verification result. Whether to perform a second programming operation or a third programming operation on the target memory cell is determined according to the first verification result. The step of performing the second programming operation or the third programming operation on the target memory cell includes: turning off a first transistor and a second transistor; and increasing a level of a passing voltage for turning on a plurality of non-target memory cells and a level of a programming voltage transmitted by the first word line.
摘要翻译： 提供了存储器阵列的编程方法，并且包括以下步骤，其中存储器阵列包括电连接到第一字线的目标存储器单元和两个外围存储器单元。 在对目标存储单元执行第一编程操作之后，验证目标存储单元和两个周边存储单元以获得第一验证结果。 根据第一验证结果确定是否对目标存储单元执行第二编程操作或第三编程操作。 对目标存储单元执行第二编程操作或第三编程操作的步骤包括：关闭第一晶体管和第二晶体管; 以及增加用于接通多个非目标存储单元的通过电压的电平以及由第一字线发送的编程电压的电平。
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公开(公告)号：US20160133718A1
公开(公告)日：2016-05-12
申请号：US14539768
申请日：2014-11-12
发明人： Guan-Wei Wu , Yao-Wen Chang , I-Chen Yang , Tao-Cheng Lu
IPC分类号： H01L29/66
CPC分类号： H01L29/6656 , H01L21/26506 , H01L21/26586 , H01L21/26593 , H01L29/1083 , H01L29/6653 , H01L29/66575 , H01L29/78
摘要： Provided is a semiconductor device. Two stack layers are disposed on a substrate of a first conductivity type. Each of stack layers includes a dielectric layer and a conductive layer. The dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. First doped region of a second conductivity type has a first dopant and is disposed in the substrate between the stack layers. A pre-amorphization implantation (PAI) region is disposed in the first doped region. A second doped region of the second conductivity type has a second dopant and is disposed in the PAI region. The first conductivity type is different from the second conductivity type. A diffusion rate of the second dopant is faster than a diffusion rate of the first dopant, and a thermal activation of the second dopant is higher than that of the first dopant.
摘要翻译： 提供一种半导体器件。 两个堆叠层设置在第一导电类型的衬底上。 每个堆叠层包括电介质层和导电层。 电介质层设置在基板上。 导电层设置在电介质层上。 第二导电类型的第一掺杂区具有第一掺杂剂并且被布置在堆叠层之间的衬底中。 在第一掺杂区域中设置预非晶化注入（PAI）区域。 第二导电类型的第二掺杂区域具有第二掺杂剂并且被布置在PAI区域中。 第一导电类型与第二导电类型不同。 第二掺杂剂的扩散速度比第一掺杂剂的扩散速度快，并且第二掺杂剂的热激活高于第一掺杂剂的扩散速率。
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公开(公告)号：US20150200306A1
公开(公告)日：2015-07-16
申请号：US14154991
申请日：2014-01-14
发明人： Guan-Wei Wu , Yao-Wen Chang , I-Chen Yang , Tao-Cheng Lu
IPC分类号： H01L29/792 , H01L21/266 , H01L21/28 , H01L29/51 , H01L29/66
CPC分类号： H01L29/792 , H01L29/40117 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66833
摘要： A non-volatile memory includes a substrate, a charge trapping structure disposed on the substrate, a buffer layer disposed on the charge trapping structure, and a plurality of conductive layers disposed on the buffer layer.
摘要翻译： 非易失性存储器包括衬底，设置在衬底上的电荷俘获结构，设置在电荷俘获结构上的缓冲层和设置在缓冲层上的多个导电层。
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公开(公告)号：US08748963B1
公开(公告)日：2014-06-10
申请号：US13707426
申请日：2012-12-06
发明人： Guan-Wei Wu , I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： H01L21/4763
CPC分类号： H01L29/792 , H01L29/42352 , H01L29/66833
摘要： A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory including a gate structure disposed on a substrate, doped regions, charge storage layers, and a first dielectric layer. There are recesses in the substrate at two sides of the gate structure. The gate structure includes a gate dielectric layer disposed on the substrate and a gate disposed on the gate dielectric layer. There is an interface between the gate dielectric layer and the substrate. The doped regions are disposed in the substrate around the recesses. The charge storage layers are disposed in the recesses, and a top surface of each of the charge storage layers is higher than the interface. The first dielectric layer is disposed between the charge storage layers and the substrate, and between the charge storage layers and the gate structure.
摘要翻译： 提供了一种非易失性存储器及其制造方法。 非易失性存储器包括设置在衬底上的栅极结构，掺杂区域，电荷存储层和第一介电层。 栅极结构两侧的基板上有凹槽。 栅极结构包括设置在衬底上的栅极电介质层和设置在栅极介电层上的栅极。 在栅介电层和衬底之间存在界面。 掺杂区域围绕凹部设置在基板中。 电荷存储层设置在凹部中，并且每个电荷存储层的顶表面高于界面。 第一介电层设置在电荷存储层与基板之间，电荷存储层与栅极结构之间。
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公开(公告)号：US20160241021A1
公开(公告)日：2016-08-18
申请号：US14624409
申请日：2015-02-17
发明人： Shih-Yu Wang , Chieh-Wei He , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An electrostatic discharge protection device that includes a plurality of voltage drop elements, an impedance element, a driving circuit, and a clamping circuit is provided. The voltage drop elements are electrically connected in series between a first line and a node, and the voltage drop elements are configured to define an activating voltage. If a signal from the first line is greater than the activating voltage, the voltage drop elements conduct the first line to the node in response to the signal from the first line. The impedance element is electrically connected between the node and a second line. The driving circuit amplifies a control signal from the node and accordingly generates a driving signal. The clamping circuit determines whether to generate a discharging path between the first line and the second line according to the driving signal.
摘要翻译： 提供了包括多个电压降元件，阻抗元件，驱动电路和钳位电路的静电放电保护器件。 电压降元件在第一线路和节点之间串联电连接，并且电压降元件被配置为限定激活电压。 如果来自第一行的信号大于激活电压，则电压降元件响应于来自第一行的信号将第一行传导到节点。 阻抗元件电连接在节点和第二线之间。 驱动电路放大来自节点的控制信号，从而产生驱动信号。 钳位电路根据驱动信号确定是否在第一线路与第二线路之间产生放电路径。
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公开(公告)号：US09208892B2
公开(公告)日：2015-12-08
申请号：US13943691
申请日：2013-07-16
发明人： Guan-Wei Wu , Yao-Wen Chang , I-Chen Yang , Tao-Cheng Lu
CPC分类号： G11C16/26 , G11C16/0475 , G11C16/3422
摘要： An operation method of a multi-level memory is provided. A first read voltage lower than a standard read voltage is applied to a doped region in a substrate at one side of a control gate of the memory, so as to determine whether a first storage position and a second storage position are both at the lowest level.
摘要翻译： 提供了多级存储器的操作方法。 将低于标准读取电压的第一读取电压施加到存储器的控制栅极的一侧的衬底中的掺杂区域，以便确定第一存储位置和第二存储位置是否都处于最低级 。
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公开(公告)号：US20140092504A1
公开(公告)日：2014-04-03
申请号：US13573738
申请日：2012-10-03
发明人： Shih-Yu Wang , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： H02H9/04
CPC分类号： H02H9/044 , H01L27/0262 , H02H9/046
摘要： An electrostatic discharge protection device including a silicon-controlled rectifier and a path switching circuit is provided. The silicon-controlled rectifier includes a first connection terminal, a second connection terminal, a first control terminal and a second control terminal, wherein the first connection terminal and the second connection terminal are respectively connected to a first line and a second line. The path switching circuit is electrically connected to the first line, the first control terminal and the second control terminal. When an input signal is supplied to the first line, the path switching circuit provides a first current path from the first line to the first control terminal in response to the input signal. When an electrostatic pulse is appeared on the first line, the path switching circuit provides a second current path from the first control terminal to the second control terminal in response to the electrostatic pulse.
摘要翻译： 提供一种包括硅控整流器和路径切换电路的静电放电保护装置。 硅控整流器包括第一连接端子，第二连接端子，第一控制端子和第二控制端子，其中第一连接端子和第二连接端子分别连接到第一线路和第二线路。 路径切换电路与第一线路，第一控制端子和第二控制端子电连接。 当输入信号被提供给第一行时，路径切换电路响应于输入信号提供从第一行到第一控制终端的第一电流路径。 当在第一线路上出现静电脉冲时，路径切换电路响应于静电脉冲提供从第一控制端子到第二控制端子的第二电流路径。
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公开(公告)号：US09509137B2
公开(公告)日：2016-11-29
申请号：US14272115
申请日：2014-05-07
发明人： Shih-Yu Wang , Tao-Cheng Lu , Yao-Wen Chang
CPC分类号： H02H9/046 , H01L27/0259
摘要： An electrostatic discharge protection device including a PNP transistor, a protection circuit and an adjustment circuit is provided. An emitter of the PNP transistor is electrically connected to a pad, and a collector of the PNP transistor is electrically connected to a ground. The protection circuit is electrically connected between a base of the PNP transistor and the ground, and provides a discharge path. When an electrostatic signal occurs on the pad, the electrostatic signal is conducted to the ground through the discharge path and the PNP transistor. The adjustment circuit is electrically connected between the emitter and the base of the PNP transistor. When a power voltage is supplied to the pad, the adjustment circuit provides a control voltage to the base of the PNP transistor according to the power voltage, so as to prevent the emitter and the base of the PNP transistor from being forward biased.
摘要翻译： 提供一种包括PNP晶体管，保护电路和调整电路的静电放电保护装置。 PNP晶体管的发射极电连接到焊盘，并且PNP晶体管的集电极电连接到地。 保护电路电连接在PNP晶体管的基极与地之间，并提供放电路径。 当在焊盘上发生静电信号时，静电信号通过放电路径和PNP晶体管传导到地面。 调节电路电连接在PNP晶体管的发射极和基极之间。 当向焊盘提供电源电压时，调节电路根据电源电压向PNP晶体管的基极提供控制电压，以防止PNP晶体管的发射极和基极正向偏置。
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公开(公告)号：US09082620B1
公开(公告)日：2015-07-14
申请号：US14150638
申请日：2014-01-08
发明人： Shih Yu Wang , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： H01L29/74 , H01L31/111 , H01L27/02 , H01L29/08
CPC分类号： H01L27/0262 , H01L27/0266 , H01L29/74 , H01L29/861
摘要： A semiconductor device includes a substrate, and first and second wells formed in the substrate. The first well has a first conductivity type. The second well has a second conductivity type different than the first conductivity type. The device includes a first heavily-doped region having the first conductivity type and a second heavily-doped region having the first conductivity type. A portion of the first heavily-doped region is formed in the first well. The second heavily-doped region is formed in the second well. The device also includes an insulating layer formed over a channel region of the substrate between the first and second heavily-doped regions, and a gate electrode formed over the insulating layer. The device further includes a terminal for coupling to a circuit being protected, and a switching circuit coupled between the terminal and the first heavily-doped region, and between the terminal and the gate electrode.
摘要翻译： 半导体器件包括衬底以及形成在衬底中的第一阱和第二阱。 第一阱具有第一导电类型。 第二阱具有与第一导电类型不同的第二导电类型。 该器件包括具有第一导电类型的第一重掺杂区和具有第一导电类型的第二重掺杂区。 在第一阱中形成第一重掺杂区的一部分。 在第二阱中形成第二重掺杂区域。 该器件还包括在第一和第二重掺杂区域之间的衬底的沟道区域上形成的绝缘层，以及形成在绝缘层上的栅电极。 该器件还包括用于耦合到被保护的电路的端子，以及耦合在端子和第一重掺杂区域之间以及端子和栅电极之间的开关电路。
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