专利检索 cpc:"H01L2924/01015" 第 4 页

31.

发明申请
SEMICONDUCTOR DEVICE 审中-公开

公开(公告)号：US20170243847A1

公开(公告)日：2017-08-24

申请号：US15587718

申请日：2017-05-05

申请人： Renesas Electronics Corporation

发明人： SHINYA SUZUKI , KIICHI MAKUTA

IPC分类号： H01L23/00 , H01L23/528 , G02F1/1345 , H01L23/522 , G02F1/133 , H01L27/02 , H01L23/532

CPC分类号： H01L24/17 , G02F1/13306 , G02F1/13452 , H01L23/49811 , H01L23/5226 , H01L23/528 , H01L23/53209 , H01L23/53214 , H01L23/53238 , H01L23/5329 , H01L24/10 , H01L24/13 , H01L24/14 , H01L27/0207 , H01L27/0248 , H01L27/0255 , H01L27/0292 , H01L2224/05124 , H01L2224/05166 , H01L2224/05184 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/13 , H01L2224/13099 , H01L2224/13144 , H01L2224/13644 , H01L2224/1403 , H01L2224/1412 , H01L2224/16 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/9211 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01025 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01055 , H01L2924/01057 , H01L2924/01059 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/013 , H01L2924/04941 , H01L2924/10161 , H01L2924/14 , H01L2924/1426 , H01L2924/15788 , H01L2924/30105 , H01L2924/00 , H01L2924/00014

摘要： To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.

32.

发明申请
Semiconductor Device 审中-公开

公开(公告)号：US20170243844A1

公开(公告)日：2017-08-24

申请号：US15591456

申请日：2017-05-10

申请人： Rohm Co., Ltd.

发明人： Tadahiro Morifuji , Shigeyuki Ueda

IPC分类号： H01L23/00

CPC分类号： H01L24/13 , H01L23/3128 , H01L23/3171 , H01L23/3192 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05014 , H01L2224/05027 , H01L2224/05541 , H01L2224/05555 , H01L2224/05557 , H01L2224/05561 , H01L2224/05583 , H01L2224/0569 , H01L2224/10122 , H01L2224/1147 , H01L2224/11902 , H01L2224/13006 , H01L2224/13023 , H01L2224/1308 , H01L2224/13099 , H01L2224/1356 , H01L2224/16 , H01L2224/8121 , H01L2224/81815 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/3512 , H01L2924/207 , H01L2924/00012 , H01L2924/00014 , H01L2924/00

摘要： Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.

33.

发明授权
3D IC method and device 有权

公开(公告)号：US09716033B2

公开(公告)日：2017-07-25

申请号：US14813972

申请日：2015-07-30

申请人： ZIPTRONIX, INC.

发明人： Paul M. Enquist , Gaius Gillman Fountain, Jr. , Qin-Yi Tong

IPC分类号： H01L23/00 , H01L21/768 , H01L27/06 , H01L23/48 , H01L25/065 , H01L25/00

CPC分类号： H01L21/76838 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/0401 , H01L2224/81121 , H01L2224/81201 , H01L2224/8123 , H01L2224/81801 , H01L2224/81894 , H01L2224/81931 , H01L2224/83894 , H01L2224/9202 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01049 , H01L2924/0105 , H01L2924/01055 , H01L2924/01059 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10329 , H01L2924/12044 , H01L2924/14 , H01L2924/19043 , H01L2924/3025 , H01L2224/81

摘要： A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.

34.

发明申请
METHOD FOR PRODUCING MEMBER FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE, AND MEMBER FOR SEMICONDUCTOR DEVICE 审中-公开

公开(公告)号：US20170207187A1

公开(公告)日：2017-07-20

申请号：US15364702

申请日：2016-11-30

申请人： FUJI ELECTRIC CO., LTD.

发明人： Shinji SANO , Yoshihiro KODAIRA , Masayuki SOUTOME , Kazunaga ONISHI

IPC分类号： H01L23/00 , H01L21/48

CPC分类号： H01L24/27 , H01L21/4853 , H01L21/4857 , H01L21/4875 , H01L23/3735 , H01L23/48 , H01L24/29 , H01L24/32 , H01L24/83 , H01L2224/2712 , H01L2224/2746 , H01L2224/291 , H01L2224/29111 , H01L2224/29116 , H01L2224/29561 , H01L2224/2969 , H01L2224/321 , H01L2224/32227 , H01L2224/32501 , H01L2224/83002 , H01L2224/83065 , H01L2224/83101 , H01L2224/83192 , H01L2224/83395 , H01L2224/83815 , H01L2924/014 , H01L2924/00014 , H01L2924/01047 , H01L2924/01029 , H01L2924/01051 , H01L2924/01028 , H01L2924/01032 , H01L2924/01015 , H01L2924/01049 , H01L2924/01083 , H01L2924/0103 , H01L2924/01082 , H01L2924/0105

摘要： There is provided a method for producing a member for semiconductor device which can reduce generation of a large number of voids in a solder-bonded portion without increasing production cost. The method includes the step of preparing a first member including a metal portion capable of being bonded by solder and the step of coating the surface of the metal portion of the first member with a treatment agent to form a treated coating which vaporizes at a temperature lower than or equal to the solidus temperature of the solder.

35.

发明授权
Rigid-flex electronic module 有权

公开(公告)号：US09674948B2

公开(公告)日：2017-06-06

申请号：US15211051

申请日：2016-07-15

申请人： GE Embedded Electronics Oy

发明人： Antti Iihola , Tuomas Waris

IPC分类号： H05K1/18 , H05K1/02 , H01L23/00 , H05K3/46 , H05K1/11

CPC分类号： H05K1/028 , H01L21/568 , H01L24/18 , H01L24/19 , H01L24/24 , H01L24/82 , H01L2224/04105 , H01L2224/12105 , H01L2224/18 , H01L2224/2919 , H01L2224/32245 , H01L2224/83005 , H01L2224/83192 , H01L2224/92144 , H01L2924/01002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01061 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/181 , H05K1/115 , H05K1/182 , H05K1/188 , H05K1/189 , H05K3/4691 , H05K2201/0187 , H05K2201/0355 , H05K2201/09127 , H05K2203/308 , H01L2924/0665 , H01L2924/00

摘要： Rigid-flex-type circuit-board structure and manufacturing method, in which a flexible membrane and a sacrificial-material piece are attached to an insulator membrane in the location of the flexible zone. An insulator layer, which encloses within itself a sacrificial-material piece is manufactured on the surface of the conductor membrane. The flexible zone is formed in such a way that an opening is made in the insulator layer, through which the sacrificial-material piece is removed. The flexible zone comprises at least part of the flexible membrane as well as conductors, which are manufactured by patterning the insulator membrane at a suitable stage in the method.

36.

发明申请
METHOD FOR PROCESSING A WAFER AND WAFER STRUCTURE 审中-公开

公开(公告)号：US20170154857A1

公开(公告)日：2017-06-01

申请号：US15430582

申请日：2017-02-13

申请人： Infineon Technologies AG

发明人： Srinivasa Reddy Yeduru , Karl Heinz Gasser , Stefan Woehlert , Karl Mayer , Francisco Javier Santos Rodriguez

IPC分类号： H01L23/00 , H01L21/288 , H01L21/683

CPC分类号： H01L23/562 , H01L21/288 , H01L21/4814 , H01L21/6835 , H01L23/49838 , H01L24/03 , H01L24/05 , H01L24/27 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/83 , H01L24/94 , H01L2221/68327 , H01L2221/6834 , H01L2224/03002 , H01L2224/04026 , H01L2224/0508 , H01L2224/05082 , H01L2224/05083 , H01L2224/05084 , H01L2224/05571 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05687 , H01L2224/27002 , H01L2224/27005 , H01L2224/2732 , H01L2224/2747 , H01L2224/29011 , H01L2224/29014 , H01L2224/29021 , H01L2224/29023 , H01L2224/29035 , H01L2224/29036 , H01L2224/29111 , H01L2224/29147 , H01L2224/2919 , H01L2224/2929 , H01L2224/29294 , H01L2224/29339 , H01L2224/29347 , H01L2224/29393 , H01L2224/32245 , H01L2224/94 , H01L2924/12042 , H01L2924/00 , H01L2924/00014 , H01L2924/01023 , H01L2924/01015 , H01L2924/04941 , H01L2924/01014 , H01L2924/01029 , H01L2224/05155 , H01L2224/05166 , H01L2224/05124 , H01L2224/05187 , H01L2924/0665 , H01L2924/01006 , H01L2924/0105 , H01L2924/01047 , H01L2924/00012 , H01L2224/03 , H01L2224/27 , H01L2924/0781 , H01L2924/07802

摘要： A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer.

37.

发明授权
Method of refining solder materials 有权

公开(公告)号：US09666547B2

公开(公告)日：2017-05-30

申请号：US12769130

申请日：2010-04-28

申请人： Martin W. Weiser , Nancy F. Dean , Brett M. Clark , Michael J. Bossio , Ronald H. Fleming , James P. Flint

发明人： Martin W. Weiser , Nancy F. Dean , Brett M. Clark , Michael J. Bossio , Ronald H. Fleming , James P. Flint

IPC分类号： H01L21/44 , H01L23/00 , B23K35/02 , C25C1/18 , H01L23/498 , B23K35/26 , C22B13/06 , H01L23/31 , H05K3/34

CPC分类号： H01L24/10 , B23K35/025 , B23K35/26 , B23K35/268 , C22B13/06 , C25C1/18 , H01L23/3128 , H01L23/49816 , H01L24/13 , H01L2224/05568 , H01L2224/05573 , H01L2224/13 , H01L2224/13099 , H01L2224/16225 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/01088 , H01L2924/01092 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H05K3/3463 , H05K3/3484 , H01L2924/00 , H01L2224/05599

摘要： The invention includes solder materials having low concentrations of alpha particle emitters, and includes methods of purification of materials to reduce a concentration of alpha particle emitters within the materials. The invention includes methods of reducing alpha particle flux in various lead-containing and lead-free materials through purification of the materials. The invention also includes methods of estimating the fractionation of a low concentration of one or more alpha particle emitters during purification of a material.

38.

发明申请
COATING AND ELECTRONIC COMPONENT 审中-公开

公开(公告)号：US20170130337A1

公开(公告)日：2017-05-11

申请号：US15415493

申请日：2017-01-25

申请人： TDK CORPORATION

发明人： Kenichi YOSHIDA , Yuhei HORIKAWA , Atsushi SATO , Hisayuki ABE

IPC分类号： C23C18/16 , H01L23/00 , C23C18/54 , C23C28/02 , C23C18/42

CPC分类号： C23C18/1655 , C23C18/1637 , C23C18/1651 , C23C18/32 , C23C18/42 , C23C18/54 , C23C28/02 , H01L24/03 , H01L24/05 , H01L2224/03464 , H01L2224/0401 , H01L2224/04042 , H01L2224/05083 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05164 , H01L2224/05644 , H01L2924/01015 , H01L2924/14 , H01L2924/00

摘要： A method of providing a coating on a conductor. The coating has a first layer containing palladium and a second layer containing gold from the conductor side. The first layer has an inner layer on the conductor side and an outer layer arranged nearer to the second layer than the inner layer, and the outer layer has a higher phosphorus concentration than the inner layer.