公开(公告)号：US20170062368A1

公开(公告)日：2017-03-02

申请号：US15246432

申请日：2016-08-24

申请人： SFA Semicon Co., Ltd.

发明人： Hyun Hak JUNG ,  Eun Dong KIM ,  Jong Won LEE ,  Jai Kyoung CHOI ,  Byeong Ho JEONG

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC分类号： H01L24/11 ,  H01L21/563 ,  H01L21/78 ,  H01L24/03 ,  H01L24/06 ,  H01L24/09 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/05082

摘要： Provided is a method of manufacturing a fan-out type wafer level package. The method includes forming a fiducial mark pattern on a frame, attaching a semiconductor die to the frame with respect to the fiducial mark pattern, encapsulating the semiconductor die with a passivation layer, for reconstituting the semiconductor die as a wafer level, and sequentially forming a metal seed layer, a redistribution layer, an under bump metal (UBM) seed layer, an UBM layer, and a solder ball on a bonding pad of the semiconductor die upward exposed by an opening region of the passivation layer to finish a fan-out type wafer level package.

摘要翻译： 提供一种制造扇出式晶片级封装的方法。 该方法包括在框架上形成基准标记图案，将半导体管芯相对于基准标记图案附接到框架，用钝化层封装半导体管芯，用于将半导体管芯重新构造为晶片级，并依次形成 金属种子层，再分配层，下凸块金属（UBM）种子层，UBM层和焊球，在半导体管芯的接合焊盘上，由钝化层的开口区域向上露出，以完成扇出 型晶圆级封装。

公开(公告)号：US20170125369A1

公开(公告)日：2017-05-04

申请号：US15291063

申请日：2016-10-11

申请人： SFA SEMICON CO., LTD.

发明人： Byeong Ho JEONG ,  Eun Dong KIM ,  Jong Won LEE ,  Hyun Hak JUNG ,  Jai Kyoung CHOI

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/16 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/10145 ,  H01L2224/10175 ,  H01L2224/11005 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1601 ,  H01L2224/16014 ,  H01L2224/16111 ,  H01L2224/16112 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/3201 ,  H01L2224/32058 ,  H01L2224/32145 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/8192 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/8388 ,  H01L2224/9211 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06558 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01044 ,  H01L2924/01051 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/095 ,  H01L2924/07025 ,  H01L2924/0715 ,  H01L2924/0685 ,  H01L2924/0695 ,  H01L2224/119 ,  H01L2224/03444 ,  H01L2224/0346 ,  H01L2224/1146 ,  H01L2224/0361 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/06 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2924/07802

摘要： The present disclosure provides a semiconductor package that prevents a bump bridge from being formed between adjacent conductive bumps to realize a fine bump pitch when each unit circuit part is directly stacked without using a printed circuit board and a method for manufacturing the same. The semiconductor package includes a first semiconductor chip structure including a first unit circuit part, a first passivation layer disposed on the first unit circuit part, and a conductive bump electrically connected to the first unit circuit part, and a second semiconductor chip structure including a second unit circuit part, a second passivation layer having a stepped portion that is recessed inward and disposed on the second unit circuit part, and a bump pad provided in the stepped portion. The first semiconductor chip structure and the second semiconductor chip structure are stacked to allow the conductive bump to be bonded to the bump pad within the stepped portion.