公开(公告)号：US09991274B2

公开(公告)日：2018-06-05

申请号：US15343591

申请日：2016-11-04

Applicant: Toshiba Memory Corporation

Inventor： Naoki Yasuda

IPC: H01L27/115 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02 ,  H01L27/11565 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/1157 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02326 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/1037 ,  H01L29/4234 ,  H01L29/511 ,  H01L29/518

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member.

公开(公告)号：US20180138189A1

公开(公告)日：2018-05-17

申请号：US15354067

申请日：2016-11-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Murshed CHOWDHURY ,  Jin LIU ,  Johann ALSMEIER

IPC: H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02494 ,  H01L21/02587 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/41741 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/512 ,  H01L29/518

Abstract: A three-dimensional memory device including self-aligned drain select level electrodes is provided. Memory stack structures extend through an alternating stack of insulating layers and spacer material layers. Each of the memory stack structures includes a memory film and a memory level channel portion. Drain select level channel portions are formed over the memory level channel portions with respective lateral shifts with respect to underlying memory stack structures. The direction of lateral shifts alternates from row to row for each row of drain select level channel portions. Drain select level gate dielectrics and drain select level gate electrodes are formed on the drain select level channel portions. Each drain select level gate electrode controls two rows of drain select level channel portions, and is laterally spaced from neighboring drain select level gate electrodes.

公开(公告)号：US20180130815A1

公开(公告)日：2018-05-10

申请号：US15867089

申请日：2018-01-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Roy Meade

IPC: H01L27/11568 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/792 ,  H01L27/115 ,  H01L27/11521 ,  H01L21/326 ,  H01L29/788

CPC classification number: H01L27/11568 ,  H01L21/02112 ,  H01L21/02318 ,  H01L21/28176 ,  H01L21/326 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4234 ,  H01L29/51 ,  H01L29/78 ,  H01L29/7883 ,  H01L29/792

Abstract: Methods for fabricating a transistor include forming a dielectric material adjacent to a semiconductor, introducing non-hydrogenous ions into the dielectric material, and forming a control gate adjacent to the dielectric material. Transistors include source/drain regions in a semiconductor, a dielectric material adjacent to the semiconductor and containing non-hydrogenous ions, and a control gate adjacent to the dielectric material

公开(公告)号：US09960175B2

公开(公告)日：2018-05-01

申请号：US15123693

申请日：2015-03-06

Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN

Inventor： Xiaogan Liang ,  Hongsuk Nam ,  Sungjin Wi ,  Mikai Chen

IPC: H01L27/115 ,  H01L27/11568 ,  H01L31/18 ,  H01L31/032 ,  H01L21/467 ,  B29C59/02 ,  H01L29/16 ,  H01L31/068 ,  H01L29/786 ,  H01L21/3065 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/11568 ,  B29C59/02 ,  H01L21/187 ,  H01L21/3065 ,  H01L21/467 ,  H01L29/1606 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/78681 ,  H01L29/792 ,  H01L31/032 ,  H01L31/068 ,  H01L31/18 ,  H01L31/1884 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method for generating a non-volatile memory device may comprise: applying plasma for a preset time period to an exposed surface of a channel of a field effect transistor such that a plurality of charge-trapping sites are formed at the channel. The channel is comprised of a multi-layer structure of atomically thin two-dimensional sheets.

公开(公告)号：US09929177B2

公开(公告)日：2018-03-27

申请号：US15404420

申请日：2017-01-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Toshiharu Nagumo

IPC: H01L29/792 ,  H01L21/336 ,  H01L27/11582 ,  H01L29/423 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/4234

Abstract: A semiconductor memory device includes a first semiconductor layer; a stacked body including a plurality of electrode layers stacked in a first direction; a metal layer provided in the first direction between the first semiconductor layer and the stacked body; a second semiconductor layer extending in the first direction through the stacked body and the metal layer, and being electrically connected to the first semiconductor layer.

公开(公告)号：US20180076214A1

公开(公告)日：2018-03-15

申请号：US15440647

申请日：2017-02-23

Applicant: Yeong Dae Lim ,  Seung Jae Jung

Inventor： Yeong Dae Lim ,  Seung Jae Jung

IPC: H01L27/11582 ,  H01L23/528 ,  H01L29/423 ,  H01L29/10 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L27/11565 ,  H01L29/1037 ,  H01L29/4234

Abstract: A semiconductor device includes a substrate, a stacked structure on the substrate, and a vertical structure in a hole passing through the stacked structure. The stacked structure includes units stacked on top of each other in a direction perpendicular to a top surface of the substrate. The units include first units and second units between the first units. Each of the first units includes a first interlayer insulating layer on a first gate, and each of the second units includes a second interlayer insulating layer on a second gate. A ratio of a thickness of the second interlayer insulating layer with respect to a thickness of the second gate is different from a ratio of a thickness of the first interlayer insulating layer with respect to a thickness of the first gate.

公开(公告)号：US20180053657A1

公开(公告)日：2018-02-22

申请号：US15663413

申请日：2017-07-28

Applicant: Cypress Semiconductor Corporation

Inventor： Fredrick B. Jenne ,  Krishnaswamy Ramkumar

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/792 ,  H01L27/11563 ,  H01L21/02 ,  G11C16/04

CPC classification number: H01L21/28282 ,  G11C16/04 ,  H01L21/022 ,  H01L21/02323 ,  H01L27/11563 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/792

Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.

公开(公告)号：US20180047452A1

公开(公告)日：2018-02-15

申请号：US15796193

申请日：2017-10-27

Applicant: Renesas Electronics Corporation

Inventor： Toshihiro TANAKA ,  Yukiko UMEMOTO ,  Mitsuru HIRAKI ,  Yutaka SHINAGAWA ,  Masamichi FUJITO ,  Kazufumi SUZUKAWA ,  Hiroyuki TANIKAWA ,  Takashi YAMAKI ,  Yoshiaki KAMIGAKI ,  Shinichi MINAMI ,  Kozo KATAYAMA ,  Nozomu MATSUZAKI

IPC: G11C16/26 ,  G11C5/02 ,  H01L29/792

CPC classification number: G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

公开(公告)号：US09842651B2

公开(公告)日：2017-12-12

申请号：US15343332

申请日：2016-11-04

Applicant: Eli Harari

Inventor： Eli Harari

IPC: G11C16/04 ,  H01L23/528 ,  H01L27/1157 ,  G11C16/28 ,  H01L29/08 ,  H01L29/16 ,  H01L29/04 ,  H01L27/11582 ,  H01L29/06 ,  H01L29/786 ,  G11C16/10 ,  H01L29/10 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/11573 ,  G11C11/56 ,  G11C16/26 ,  G11C16/34 ,  H01L27/06 ,  H01L29/792

CPC classification number: G11C16/0466 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3427 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28282 ,  H01L21/32133 ,  H01L21/76892 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6675 ,  H01L29/66833 ,  H01L29/78642 ,  H01L29/7926

Abstract: A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.

公开(公告)号：US09831268B2

公开(公告)日：2017-11-28

申请号：US15282010

申请日：2016-09-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Johann Alsmeier

IPC: H01L21/336 ,  H01L27/11582 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11517 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/7889 ,  H01L29/7926

Abstract: A method of making a monolithic three dimensional NAND string is provided. A stack of alternating layers of a first material and a second material different from the first material is formed over a substrate. The stack is etched to form at least one opening in the stack. A charge storage material layer is formed on a sidewall of the at least one opening. A tunnel dielectric layer is formed on the charge storage material layer in the at least one opening. A semiconductor channel material is formed on the tunnel dielectric layer in the at least one opening. The first material layers are selectively removed to expose side wall of the charge storage material layer. A blocking dielectric is formed on the exposed side wall of the charge storage material layer. Control gates are formed on the blocking dielectric.