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公开(公告)号：US20180047452A1
公开(公告)日：2018-02-15
申请号：US15796193
申请日：2017-10-27
Applicant: Renesas Electronics Corporation
Inventor： Toshihiro TANAKA , Yukiko UMEMOTO , Mitsuru HIRAKI , Yutaka SHINAGAWA , Masamichi FUJITO , Kazufumi SUZUKAWA , Hiroyuki TANIKAWA , Takashi YAMAKI , Yoshiaki KAMIGAKI , Shinichi MINAMI , Kozo KATAYAMA , Nozomu MATSUZAKI
IPC: G11C16/26 , G11C5/02 , H01L29/792
CPC classification number: G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
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公开(公告)号：US20180374542A1
公开(公告)日：2018-12-27
申请号：US16116893
申请日：2018-08-29
Applicant: Renesas Electronics Corporation
Inventor： Toshihiro TANAKA , Yukiko UMEMOTO , Mitsuru HIRAKI , Yutaka SHINAGAWA , Masamichi FUJITO , Kazufumi SUZUKAWA , Hiroyuki TANIKAWA , Takashi YAMAKI , Yoshiaki KAMIGAKI , Shinichi MINAMI , Kozo KATAYAMA , Nozomu MATSUZAKI
IPC: G11C16/26 , G11C16/30 , G11C16/04 , G11C8/08 , G11C5/02 , H01L21/28 , G11C16/24 , H01L29/792 , H01L29/788 , H01L29/66 , H01L29/423 , H01L27/11546 , H01L27/11526 , H01L27/11521 , H01L27/115 , H01L27/105 , G11C16/08
CPC classification number: G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
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公开(公告)号：US20130235668A1
公开(公告)日：2013-09-12
申请号：US13867055
申请日：2013-04-20
Inventor： Toshihiro TANAKA , Yukiko UMEMOTO , Mitsuru HIRAKI , Yutaka SHINAGAWA , Masamichi FUJITO , Kazufumi SUZUKAWA , Hiroyuki TANIKAWA , Takashi YAMAKI , Yoshiaki KAMIGAKI , Shinichi MINAMI , Kozo KATAYAMA , Nozomu MATSUZAKI
CPC classification number: G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
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公开(公告)号：US20150111357A1
公开(公告)日：2015-04-23
申请号：US14586452
申请日：2014-12-30
Applicant: Renesas Electronics Corporation
Inventor： Eiji TSUKUDA , Kozo KATAYAMA , Kenichiro SONODA , Tatsuya KUNIKIYO
IPC: H01L29/66 , H01L27/115
CPC classification number: H01L29/66545 , H01L21/283 , H01L27/115 , H01L27/11563 , H01L27/11568 , H01L27/11573 , H01L29/4234 , H01L29/66833 , H01L29/792
Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability.First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.
Abstract translation: 提供包括具有更高可靠性的存储单元的半导体器件的制造方法。 形成存储单元形成区域中的第一和第二堆叠结构，以在晶体管形成区域中具有比第三层叠结构更大的高度，然后形成层间绝缘层以覆盖这些堆叠结构，然后进行抛光。
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公开(公告)号：US20140213030A1
公开(公告)日：2014-07-31
申请号：US14155961
申请日：2014-01-15
Applicant: Renesas Electronics Corporation
Inventor： Eiji TSUKUDA , Kozo KATAYAMA , Kenichiro SONODA , Tatsuya KUNIKIYO
IPC: H01L29/66
CPC classification number: H01L29/66545 , H01L21/283 , H01L27/115 , H01L27/11563 , H01L27/11568 , H01L27/11573 , H01L29/4234 , H01L29/66833 , H01L29/792
Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability.First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.
Abstract translation: 提供包括具有更高可靠性的存储单元的半导体器件的制造方法。 形成存储单元形成区域中的第一和第二堆叠结构，以在晶体管形成区域中具有比第三层叠结构更大的高度，然后形成层间绝缘层以覆盖这些堆叠结构，然后进行抛光。
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公开(公告)号：US20160336074A1
公开(公告)日：2016-11-17
申请号：US15224669
申请日：2016-08-01
Applicant: Renesas Electronics Corporation
Inventor： Toshihiro TANAKA , Yukiko UMEMOTO , Mitsuru HIRAKI , Yutaka SHINAGAWA , Masamichi FUJITO , Kazufumi SUZUKAWA , Hiroyuki TANIKAWA , Takashi YAMAKI , Yoshiaki KAMIGAKI , Shinichi MINAMI , Kozo KATAYAMA , Nozomu MATSUZAKI
IPC: G11C16/26 , H01L27/115 , H01L21/28 , G11C16/04 , G11C16/24
CPC classification number: G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
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公开(公告)号：US20160133641A1
公开(公告)日：2016-05-12
申请号：US14997515
申请日：2016-01-16
Applicant: Renesas Electronics Corporation
Inventor： Naohiro HOSODA , Daisuke OKADA , Kozo KATAYAMA
IPC: H01L27/115 , H01L29/792 , H01L29/423
CPC classification number: H01L27/11568 , H01L27/115 , H01L29/42344 , H01L29/42364 , H01L29/66833 , H01L29/792
Abstract: A semiconductor device of the present invention has a first insulating film formed between a control gate electrode and a semiconductor substrate and a second insulating film formed between a memory gate electrode and the semiconductor substrate and between the control gate electrode and the memory gate electrode, the second insulating film having a charge accumulating part therein. The second insulating film has a first film, a second film serving as a charge accumulating part disposed on the first film, and a third film disposed on the second film. The third film has a sidewall film positioned between the control gate electrode and the memory gate electrode and a deposited film positioned between the memory gate electrode and the semiconductor substrate. In this structure, the distance at a corner part of the second insulating film can be increased, and electric-field concentration can be reduced.
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公开(公告)号：US20160093716A1
公开(公告)日：2016-03-31
申请号：US14877521
申请日：2015-10-07
Applicant: Renesas Electronics Corporation
Inventor： Eiji TSUKUDA , Kozo KATAYAMA , Kenichiro SONODA , Tatsuya KUNIKIYO
IPC: H01L29/66 , H01L27/115 , H01L21/283
CPC classification number: H01L29/66545 , H01L21/283 , H01L27/115 , H01L27/11563 , H01L27/11568 , H01L27/11573 , H01L29/4234 , H01L29/66833 , H01L29/792
Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.
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公开(公告)号：US20140198577A1
公开(公告)日：2014-07-17
申请号：US14214969
申请日：2014-03-16
Inventor： Toshihiro TANAKA , Yukiko UMEMOTO , Mitsuru HIRAKI , Yutaka SHINAGAWA , Masamichi FUJITO , Kazufumi SUZUKAWA , Hiroyuki TANIKAWA , Takashi YAMAKI , Yoshiaki KAMIGAKI , Shinichi MINAMI , Kozo KATAYAMA , Nozomu MATSUZAKI
IPC: G11C16/26
CPC classification number: G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
Abstract translation: 半导体器件包括多个非易失性存储单元（1）。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。 第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。 第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc
