公开(公告)号：US20140357025A1

公开(公告)日：2014-12-04

申请号：US14462776

申请日：2014-08-19

Applicant: Sony Corporation

Inventor： Satoru Wakiyama

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/544

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11015 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/14131 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/26135 ,  H01L2224/26145 ,  H01L2224/26165 ,  H01L2224/27334 ,  H01L2224/27416 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48 ,  H01L2224/73104 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/81903 ,  H01L2224/83007 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83141 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device including a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

Abstract translation: 一种包括半导体元件的半导体器件; 形成在半导体元件上的焊盘电极; 形成在半导体元件上的对准标记; 形成在焊盘电极上的连接电极; 以及形成为覆盖连接电极的底部填充树脂。 来自半导体元件的对准标记的高度大于连接电极的高度。

公开(公告)号：US20140110789A1

公开(公告)日：2014-04-24

申请号：US14143207

申请日：2013-12-30

Applicant: Renesas Electronics Corporation

Inventor： Masami KOKETSU ,  Toshiaki SAWADA

IPC: H01L23/544 ,  H01L23/535

CPC classification number: H01L23/544 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L23/585 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/16 ,  H01L2224/8113 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01054 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/1433 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract translation: 通过提高对准标记的可视性，提供能够高精度地定位半导体芯片和安装基板的技术。 在构成LCD驱动器的半导体芯片中，在半导体衬底上的对准标记形成区域中形成标记。 标记形成在与集成电路形成区域中的最上层布线（第三层布线）相同的层中。 然后，在标记的下层和标记周围的背景区域形成图案。 此时，图案P1a形成在与第二层布线相同的层中，并且图案P1b形成在与第一层布线相同的层中。 此外，图案P2形成在与栅极电极相同的层中，并且图案P3形成在与元件隔离区域相同的层中。

公开(公告)号：US20130307036A1

公开(公告)日：2013-11-21

申请号：US13840625

申请日：2013-03-15

Applicant: Renesas Electronics Corporation

Inventor： Masami KOKETSU ,  Toshiaki SAWADA

IPC: H01L23/544 ,  H01L29/78

CPC classification number: H01L23/544 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L23/585 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/16 ,  H01L2224/8113 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01054 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/1433 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00

Abstract: In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern Pla is formed in the same layer as that of a second layer wiring and the pattern Pib is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract translation: 在构成LCD驱动器的半导体芯片中，在半导体衬底上的对准标记形成区域中形成标记。 标记形成在与集成电路形成区域中的最上层布线（第三层布线）相同的层中。 然后，在标记的下层和标记周围的背景区域形成图案。 此时，图案Pla形成在与第二层布线相同的层中，并且图案Pib形成在与第一层布线相同的层中。 此外，图案P2形成在与栅极电极相同的层中，并且图案P3形成在与元件隔离区域相同的层中。

公开(公告)号：US08541887B2

公开(公告)日：2013-09-24

申请号：US12875710

申请日：2010-09-03

Applicant: Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

Inventor： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

IPC: H01L25/00

CPC classification number: H01L21/6835 ,  H01L21/563 ,  H01L23/3192 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2746 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32148 ,  H01L2224/81121 ,  H01L2224/8113 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82005 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83444 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2221/68304

Abstract: A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. Each layer portion includes a semiconductor chip having a first surface and a second surface opposite thereto, and includes a plurality of electrodes. The electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the electrodes of the first layer portion, and the second terminals are formed by using the electrodes of the second layer portion.

Abstract translation: 分层芯片封装包括主体和布线，其包括布置在主体的侧表面上的多根导线。 主体包括：主要部分，包括第一和第二层部分; 以及多个第一和第二端子，其分别设置在主要部分的顶表面和底表面上，并且电连接到多个导线。 每个层部分包括具有第一表面和与其相对的第二表面的半导体芯片，并且包括多个电极。 电极设置在与第二表面相对的半导体芯片的一侧上。 第一和第二层部分彼此接合，使得相应的第二表面彼此面对。 通过使用第一层部分的电极形成第一端子，并且通过使用第二层部分的电极形成第二端子。

公开(公告)号：US20120248603A1

公开(公告)日：2012-10-04

申请号：US13525122

申请日：2012-06-15

Applicant: MASAMI KOKETSU ,  Toshiaki Sawada

Inventor： MASAMI KOKETSU ,  Toshiaki Sawada

IPC: H01L23/498 ,  H01L23/48

CPC classification number: H01L23/544 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L23/585 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/16 ,  H01L2224/8113 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01054 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/1433 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract translation: 通过提高对准标记的可视性，提供能够高精度地定位半导体芯片和安装基板的技术。 在构成LCD驱动器的半导体芯片中，在半导体衬底上的对准标记形成区域中形成标记。 标记形成在与集成电路形成区域中的最上层布线（第三层布线）相同的层中。 然后，在标记的下层和标记周围的背景区域形成图案。 此时，图案P1a形成在与第二层布线相同的层中，并且图案P1b形成在与第一层布线相同的层中。 此外，图案P2形成在与栅极电极相同的层中，并且图案P3形成在与元件隔离区域相同的层中。

公开(公告)号：US20120232686A1

公开(公告)日：2012-09-13

申请号：US13042494

申请日：2011-03-08

Applicant: Yongchun Xin ,  Xu Ouyang ,  Yunsheng Song ,  Tso-Hui Ting

Inventor： Yongchun Xin ,  Xu Ouyang ,  Yunsheng Song ,  Tso-Hui Ting

IPC: G05D3/00 ,  G06F15/00 ,  G01B9/02

CPC classification number: H01L21/681 ,  G01B9/02091 ,  H01L23/544 ,  H01L24/75 ,  H01L24/81 ,  H01L24/94 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/75753 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2224/81

Abstract: A system for performing alignment of two wafers is disclosed. The system comprises an optical coherence tomography system and a wafer alignment system. The wafer alignment system is configured and disposed to control the relative position of a first wafer and a second wafer. The optical coherence tomography system is configured and disposed to compute coordinate data for a plurality of alignment marks on the first wafer and second wafer, and send that coordinate data to the wafer alignment system

Abstract translation: 公开了一种用于执行两个晶片对准的系统。 该系统包括光学相干断层摄影系统和晶片对准系统。 晶片对准系统被配置和设置以控制第一晶片和第二晶片的相对位置。 光学相干断层摄影系统被配置和设置为计算第一晶片和第二晶片上的多个对准标记的坐标数据，并将该坐标数据发送到晶片对准系统

公开(公告)号：US20120153462A1

公开(公告)日：2012-06-21

申请号：US13312565

申请日：2011-12-06

Applicant: Satoru Wakiyama

Inventor： Satoru Wakiyama

IPC: H01L23/498 ,  H01L23/52 ,  H01L21/50 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11015 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/14131 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/26135 ,  H01L2224/26145 ,  H01L2224/26165 ,  H01L2224/27334 ,  H01L2224/27416 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48 ,  H01L2224/73104 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/81903 ,  H01L2224/83007 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83141 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

Abstract translation: 半导体器件包括半导体元件; 形成在半导体元件上的焊盘电极; 形成在半导体元件上的对准标记; 形成在焊盘电极上的连接电极; 以及形成为覆盖连接电极的底部填充树脂。 来自半导体元件的对准标记的高度大于连接电极的高度。

公开(公告)号：US07618847B2

公开(公告)日：2009-11-17

申请号：US12187622

申请日：2008-08-07

Applicant: Hiroyuki Tenmei ,  Kunihiko Nishi ,  Yasuhiro Naka ,  Nae Hisano ,  Hiroaki Ikeda ,  Masakazu Ishino

Inventor： Hiroyuki Tenmei ,  Kunihiko Nishi ,  Yasuhiro Naka ,  Nae Hisano ,  Hiroaki Ikeda ,  Masakazu Ishino

IPC: H01L21/00

CPC classification number: H01L24/73 ,  H01L21/76898 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/75753 ,  H01L2224/8113 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/83871 ,  H01L2224/83907 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/27

Abstract: A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the principal surfaces. However, there is a problem of poor electrical coupling due to displacement of the bumps and the pads when bonded together. The present invention solves such a problem by conducting temporary positioning of the silicon wafers, adjusting the positions of the coupling bumps and pads while confirming the positions by a method such as x-ray capable of passing through the silicon wafers, and bonding the bumps and the pads together while hardening an interlayer adhesive provided between the principal surfaces of the silicon wafers by thermocompression.

Abstract translation: 提供半导体衬底的接合方法（三维安装），以通过施加的粘合剂顺序地接合形成有耦合凸块的硅晶片的主表面和形成有焊盘的另一个硅晶片的主表面 到至少一个主表面。 然而，由于当焊接在一起时由于凸起和焊盘的位移而存在差的电耦合的问题。 本发明通过进行硅晶片的临时定位来解决这样的问题，通过诸如能够通过硅晶片的x射线的方法确认位置来确定位置，并且将凸块和 一边通过热压而使设置在硅晶片的主表面之间的层间粘合剂硬化。

公开(公告)号：US07514295B2

公开(公告)日：2009-04-07

申请号：US11196487

申请日：2005-08-04

Applicant: Masataka Mizukoshi ,  Nobuhiro Imaizumi ,  Yoshikatsu Ishizuki

Inventor： Masataka Mizukoshi ,  Nobuhiro Imaizumi ,  Yoshikatsu Ishizuki

IPC: H01L21/60

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L24/02 ,  H01L24/06 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05578 ,  H01L2224/06102 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/13028 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/1357 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/13669 ,  H01L2224/16106 ,  H01L2224/16225 ,  H01L2224/2784 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/83121 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2924/00 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/13091 ,  H01L2924/19041 ,  Y10T29/49126 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099

Abstract: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.

Abstract translation: 本发明实现了一种高可靠性的半导体器件，其允许在低负载和低成本下形成具有均匀高度，平坦和平滑的金属端子并且以低损伤安装。 电极5和绝缘膜6均由具有固体特性的材料形成，并且在室温下不显示粘合性，并且在不低于第一温度的温度下显示粘附性，并且在不低于 第二温度高于第一温度。 半导体芯片1a的电极5和绝缘膜6的表面与硬质切削工具一样平坦化，如金刚石等。

公开(公告)号：US20080135956A1

公开(公告)日：2008-06-12

申请号：US11637668

申请日：2006-12-12

Applicant: William Hullinger Huber ,  Francis Johnson

Inventor： William Hullinger Huber ,  Francis Johnson

IPC: H01L29/82 ,  B32B3/00 ,  B05D5/12

CPC classification number: H01F1/26 ,  H01F1/083 ,  H01F1/113 ,  H01F1/37 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/93 ,  H01L24/95 ,  H01L25/50 ,  H01L2224/32014 ,  H01L2224/32055 ,  H01L2224/81121 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/83121 ,  H01L2224/83136 ,  H01L2224/83143 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83801 ,  H01L2224/95085 ,  H01L2224/95144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01064 ,  H01L2924/01065 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  Y10T428/24917 ,  H01L2924/01026 ,  H01L2924/01014 ,  H01L2924/01032 ,  H01L2924/01049 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A functional block for assembly includes at least one element and a magnetic film attached to the element and having a magnetic remanence (MR/MS) of less than about 0.2, having a coercive field (Hc) of less than about 100 Oersteds (100 Oe) and having a permeability (μ) of greater than about two (2). At least one element is selected from the group consisting of a semiconductor device, a passive element, a photonic bandgap element, a luminescent material, a sensor, a micro-electrical mechanical system (MEMS), an energy harvesting device and combinations thereof. An article for assembly includes a substrate and a patterned magnetic film disposed on the substrate and defining at least one receptor site. The patterned magnetic film is magnetized primarily in a longitudinal direction and is characterized by a BH product of greater than about 1 megaGauss Oe.

Abstract translation: 用于组装的功能块包括至少一个元件和附着到该元件的磁性薄膜，并具有小于约0.2的磁性剩磁（M / R / M） 具有小于约100奥斯特（100Oe）并且具有大于约二（2）的磁导率（μ）的矫顽场（HCC）。 选自由半导体器件，无源元件，光子带隙元件，发光材料，传感器，微机电系统（MEMS），能量收集器件及其组合组成的组中的至少一个元件。 用于组装的制品包括基底和设置在基底上并限定至少一个受体部位的图案化磁性膜。 图案化磁性膜主要在纵向上被磁化，其特征在于大于约1兆高斯Oe的BH产物。