公开(公告)号：US20150048519A1

公开(公告)日：2015-02-19

申请号：US14180327

申请日：2014-02-13

Applicant: SK HYNIX INC.

Inventor： Jin Woo PARK ,  Sang Gyu LEE

IPC: H01L23/522 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L24/97 ,  H01L21/7684 ,  H01L21/76897 ,  H01L21/76898 ,  H01L21/784 ,  H01L23/3107 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

Abstract: A semiconductor device includes a via electrode penetrating a substrate and a back-side molding layer covering a back-side surface of the substrate. The back-side molding layer contacts a sidewall of a back-side end portion of the via electrode, which is a portion of the via electrode that protrudes from the back-side surface of the substrate.

Abstract translation: 半导体器件包括穿透基板的通路电极和覆盖基板的背面的背面成型层。 背面成型层与作为从基板的背面突出的通孔电极的一部分的通路电极的背面侧端部的侧壁接触。

公开(公告)号：US20130134580A1

公开(公告)日：2013-05-30

申请号：US13307849

申请日：2011-11-30

Applicant: Xusheng Bao ,  Ma Phoo Pwint Hlaing ,  Jian Zuo

Inventor： Xusheng Bao ,  Ma Phoo Pwint Hlaing ,  Jian Zuo

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L24/14 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02125 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05173 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05583 ,  H01L2224/05613 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05687 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11901 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/14131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/0231 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/04953 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2924/01023 ,  H01L2924/04941 ,  H01L2924/01082 ,  H01L2224/11849 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.

Abstract translation: 半导体器件具有带有多个半导体管芯的半导体晶片。 在晶片的表面上形成第一导电层。 在晶片和第一导电层的表面上形成第一绝缘层。 第二导电层具有形成在第一绝缘层上的第一和第二部分。 在第一绝缘层和第二导电层上形成第二绝缘层。 UBM层形成在第二绝缘层和第二导电层的第一段之上。 在UBM层上形成第一凸点。 第一凸起电连接到第二段并与第二导电层的第一段电隔离。 第二凸起形成在晶片的表面上并电连接到第二导电层的第一段。

公开(公告)号：US20120068306A1

公开(公告)日：2012-03-22

申请号：US13230875

申请日：2011-09-13

Applicant: Sang-Sub SONG ,  Sung-Hoon Chun ,  Sang-Ho An ,  Joon-Young Oh ,  Dong-Ok Kwak

Inventor： Sang-Sub SONG ,  Sung-Hoon Chun ,  Sang-Ho An ,  Joon-Young Oh ,  Dong-Ok Kwak

IPC: H01L27/08

CPC classification number: H01L23/50 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/16 ,  H01L28/60 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/06139 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor package includes a packaging substrate including a first bond finger and a second bond finger, a first semiconductor chip mounted on the packaging substrate, and including a first chip pad and a second chip pad, the first bond finger being electrically connected to the first chip pad by a first bonding wire, and the second bond finger being electrically connected to the second chip pad by a second bonding wire, and a first decoupling semiconductor capacitor mounted on the first semiconductor chip, and including a first capacitor pad, the first capacitor pad being electrically connected to the second chip pad.

Abstract translation: 半导体封装包括包括第一键合指状物和第二键合指状物的封装衬底，安装在封装衬底上的第一半导体芯片，并且包括第一芯片焊盘和第二芯片焊盘，第一键合指状电连接到第一键 并且所述第二接合指状物通过第二接合线电连接到所述第二芯片焊盘，以及安装在所述第一半导体芯片上的第一解耦半导体电容器，并且包括第一电容器焊盘，所述第一电容器 焊盘电连接到第二芯片焊盘。

公开(公告)号：US08058564B2

公开(公告)日：2011-11-15

申请号：US12043689

申请日：2008-03-06

Applicant: Wen-Hung Hu

Inventor： Wen-Hung Hu

IPC: H05K1/09

CPC classification number: H05K3/3452 ,  H01L23/49811 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05601 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/0562 ,  H01L2224/05623 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/0567 ,  H01L2224/05671 ,  H01L2224/16 ,  H01L2924/01079 ,  H05K3/0023 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3473 ,  H05K2203/054 ,  H05K2203/0594 ,  H01L2924/00014 ,  H01L2924/01024 ,  H01L2924/01082 ,  H01L2924/013

Abstract: A circuit board surface structure includes a circuit board having at least one surface provided with a plurality of electrically connecting pads, an insulating protective layer characterized by photosensitivity and solder resisting and formed on the circuit board, and a plurality of openings formed in the insulating protective layer to expose the electrical connecting pads on the circuit board and tapered upward; and a conductive element formed in the opening, so as to increase the contact area and reinforce bonding between the electrically connecting pads and the conductive element.

Abstract translation: 电路板表面结构包括具有设置有多个电连接焊盘的至少一个表面的电路板，形成在电路板上的光敏性和阻焊性特征的绝缘保护层，以及形成在绝缘保护层中的多个开口 以暴露电路板上的电连接焊盘并向上锥形; 以及形成在开口中的导电元件，以便增加接触面积并加强电连接焊盘和导电元件之间的接合。

公开(公告)号：US20110031617A1

公开(公告)日：2011-02-10

申请号：US12908777

申请日：2010-10-20

Applicant: Wen-Hung Hu

Inventor： Wen-Hung Hu

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/498 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05618 ,  H01L2224/0562 ,  H01L2224/05623 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package.

Abstract translation: 公开了一种半导体封装基板结构及其制造方法。 该结构包括具有形成在其至少一个表面上的多个电连接焊盘的基板; 多个电镀导电柱，每个覆盖相应的一个电连接焊盘和形成在该基板的表面上的绝缘保护层，并且具有用于使电镀的导电柱露出的露出部分。 本发明允许电镀导电柱之间的间隔最小化，产生集中应力和避免底部填充物的溢出，以及制造的封装的整体高度的降低。

公开(公告)号：US07675183B2

公开(公告)日：2010-03-09

申请号：US12081818

申请日：2008-04-22

Applicant: Hiroshi Toyoda ,  Mitsuhiro Nakao ,  Masahiko Hasunuma ,  Hisashi Kaneko ,  Atsuko Sakata ,  Toshiaki Komukai

Inventor： Hiroshi Toyoda ,  Mitsuhiro Nakao ,  Masahiko Hasunuma ,  Hisashi Kaneko ,  Atsuko Sakata ,  Toshiaki Komukai

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76846 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76886 ,  H01L21/76888 ,  H01L22/32 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05093 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05546 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05605 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/0562 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/45105 ,  H01L2224/45109 ,  H01L2224/45111 ,  H01L2224/45113 ,  H01L2224/45116 ,  H01L2224/4512 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48505 ,  H01L2224/48611 ,  H01L2224/48616 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48711 ,  H01L2224/48716 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48799 ,  H01L2224/48805 ,  H01L2224/48811 ,  H01L2224/48813 ,  H01L2224/48816 ,  H01L2224/4882 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/85375 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2224/05609 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2224/48713 ,  H01L2224/48705 ,  H01L2224/4872 ,  H01L2224/48605 ,  H01L2224/48613 ,  H01L2224/4862 ,  H01L2924/00015

Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.

Abstract translation: 一种半导体器件，其由形成在半导体衬底上的铜布线层构成，该电极层与铜布线层电连接并具有合金，所述焊接电极层含有铜和氧化倾向高于铜的金属 形成为延伸到底表面，并且具有延伸到焊盘电极层的开口的绝缘保护膜。

公开(公告)号：US20080217047A1

公开(公告)日：2008-09-11

申请号：US12043689

申请日：2008-03-06

Applicant: Wen-Hung Hu

Inventor： Wen-Hung Hu

IPC: H05K1/09 ,  H05K1/00 ,  H05K1/11

CPC classification number: H05K3/3452 ,  H01L23/49811 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05601 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/0562 ,  H01L2224/05623 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/0567 ,  H01L2224/05671 ,  H01L2224/16 ,  H01L2924/01079 ,  H05K3/0023 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3473 ,  H05K2203/054 ,  H05K2203/0594 ,  H01L2924/00014 ,  H01L2924/01024 ,  H01L2924/01082 ,  H01L2924/013

Abstract: A circuit board surface structure includes a circuit board having at least one surface provided with a plurality of electrically connecting pads, an insulating protective layer characterized by photosensitivity and solder resisting and formed on the circuit board, and a plurality of openings formed in the insulating protective layer to expose the electrical connecting pads on the circuit board and tapered upward; and a conductive element formed in the opening, so as to increase the contact area and reinforce bonding between the electrically connecting pads and the conductive element.

Abstract translation: 电路板表面结构包括具有设置有多个电连接焊盘的至少一个表面的电路板，形成在电路板上的光敏性和阻焊性特征的绝缘保护层，以及形成在绝缘保护层中的多个开口 以暴露电路板上的电连接焊盘并向上锥形; 以及形成在开口中的导电元件，以便增加接触面积并加强电连接焊盘和导电元件之间的接合。

公开(公告)号：US06448647B1

公开(公告)日：2002-09-10

申请号：US09090633

申请日：1998-06-04

Applicant: Hideyuki Kurita ,  Masahiro Fujimoto

Inventor： Hideyuki Kurita ,  Masahiro Fujimoto

IPC: H01L2348

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/05613 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/112 ,  H05K3/3436 ,  H05K3/3478 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09827 ,  H05K2203/041 ,  H05K2203/0594 ,  Y02P70/613 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: It is an object of the present invention to provide a BGA package substrate capable of forming a thin and light BGA package which causes no crack in solder balls during temperature cycling tests and which permits fine-pitch packaging. According to the present invention, a conductive pattern 3 is formed on a solder resist layer 2 made of polyimide and a cover film 4 is formed on the conductive pattern 3. The conductive pattern 3 includes a land 3a for connection to a mother board and a bonding pad 3b for connection to an IC. The solder resist layer 2 has an opening 5 to leave an overlap on the periphery of the land 3a, and an end of the opening 5 is tapered. A solder ball 6 is formed on the land 3a.

Abstract translation: 本发明的目的是提供一种能够形成薄且轻的BGA封装的BGA封装基板，其在温度循环测试期间不会在焊球中产生裂纹并且允许精细间距封装。根据本发明，导电 图案3形成在由聚酰亚胺制成的阻焊层2上，并且在导电图案3上形成覆盖膜4.导电图案3包括用于连接到母板的焊盘3a和用于连接到IC的焊盘3b 。 阻焊层2具有开口5，以在焊盘3a的周围留下重叠，并且开口5的端部是锥形的。 焊盘3形成在焊盘3a上。

公开(公告)号：US5829125A

公开(公告)日：1998-11-03

申请号：US698163

申请日：1996-08-07

Applicant: Masayuki Fujimoto ,  Matsuo Nakazawa ,  Hiroshi Takahashi ,  Kazutaka Suzuki ,  Koichiro Isuzuku

Inventor： Masayuki Fujimoto ,  Matsuo Nakazawa ,  Hiroshi Takahashi ,  Kazutaka Suzuki ,  Koichiro Isuzuku

IPC: B23K1/005 ,  H01L21/60 ,  H01L23/13 ,  H01L23/485 ,  H01L25/18 ,  H05K3/34

CPC classification number: H01L23/13 ,  B23K1/0056 ,  H01L24/05 ,  H01L24/81 ,  H01L25/18 ,  H05K3/3494 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05111 ,  H01L2224/05118 ,  H01L2224/05566 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/05609 ,  H01L2224/05613 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08057 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14155 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/75 ,  H01L2224/75252 ,  H01L2224/75262 ,  H01L2224/81026 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81224 ,  H01L2224/81385 ,  H01L2224/81405 ,  H01L2224/81409 ,  H01L2224/81413 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/8184 ,  H01L2224/81868 ,  H01L2224/81874 ,  H01L2224/83224 ,  H01L24/13 ,  H01L24/75 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/351 ,  H05K2201/0108 ,  H05K2201/0112 ,  H05K2203/107 ,  H05K3/3431 ,  Y10T29/49144

Abstract: The present invention relates to a method of manufacturing a circuit module through the use of a wireless bonding technique. In this invention, in order to achieve component assembly without experiencing thermal and mechanical stresses, in the circuit module manufacturing method in which an external electrode of a component and a conductor of a substrate are connected with each other according to the wireless bonding technique, the substrate has a laser beam transmissible property, and after the component is placed on an assembly surface of the substrate, a laser beam is applied from a surface of the substrate opposite to the assembly surface thereof to a connecting spot. The laser beam passing through the substrate heats the connecting spot so that the connection between the external electrode of the component and the conductor of the substrate is made by phase transition or diffusion.

Abstract translation: 本发明涉及通过使用无线接合技术制造电路模块的方法。 在本发明中，为了实现不经受热和机械应力的部件组装，在根据无线接合技术将部件的外部电极和基板的导体彼此连接的电路模块制造方法中， 基板具有激光束透射性质，并且在将部件放置在基板的组装表面上之后，将激光束从与其组装表面相对的基板的表面施加到连接点。 通过基板的激光束加热连接点，使得部件的外部电极与基板的导体之间的连接通过相变或扩散来制造。

公开(公告)号：US20240363566A1

公开(公告)日：2024-10-31

申请号：US18139896

申请日：2023-04-26

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Wang Gu Lee ,  Ju Hong Shin ,  Ji Hun Lee

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/08 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/80 ,  H01L23/49894 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03845 ,  H01L2224/05018 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/80013 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80815 ,  H01L2224/80896 ,  H01L2224/80905 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0504 ,  H01L2924/05442 ,  H01L2924/059

Abstract: In one example, an electronic device, comprises a first component comprising a first component inner side and a first component backside, a first component inner terminal, a first component dielectric at the first component inner side, and a first component interconnect coupled with the first component inner terminal. The electronic device comprises a second component over the first component and comprising a second component inner side facing the first component inner side, and a second component backside, a second component inner terminal, a second component dielectric at the second component inner side, and a second component interconnect coupled with the second component inner terminal. The first component dielectric and the second component dielectric comprise an inorganic material, the first component dielectric is coupled with the second component dielectric, and the first component interconnect is coupled with the second component interconnect. Other examples and related methods are also disclosed herein.