公开(公告)号：US20170338171A1

公开(公告)日：2017-11-23

申请号：US15161077

申请日：2016-05-20

申请人： Infineon Technologies Americas Corp.

发明人： Eung San Cho ,  Parviz Parto

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L25/16 ,  H01L49/02

CPC分类号： H01L23/49575 ,  H01L21/4853 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49551 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L28/10 ,  H01L2224/13101 ,  H01L2224/16245 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1425 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/014 ,  H01L2924/00014

摘要： In one implementation, a semiconductor package includes an integrated circuit (IC) flip chip mounted on a first patterned conductive carrier, a second patterned conductive carrier situated over the IC, and a magnetic material situated over the second patterned conductive carrier. The semiconductor package also includes a third patterned conductive carrier situated over the magnetic material. The second patterned conductive carrier and the third patterned conductive carrier are electrically coupled so as to form windings of an integrated inductor in the semiconductor package.

公开(公告)号：US20170317041A1

公开(公告)日：2017-11-02

申请号：US15263391

申请日：2016-09-13

申请人： Powertech Technology Inc.

发明人： Yun-Hsin Yeh ,  Hung-Hsin Hsu

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

CPC分类号： H01L24/06 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/105 ,  H01L2224/02317 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

摘要： A stackable semiconductor package and manufacturing method thereof are provided. The stackable semiconductor package includes carrier, first RDL, encapsulation layer, vertical interposers, second RDL, and chip. The carrier has first surface in which the first RDL and the encapsulation layer are formed thereon. The first RDL includes first pads and second pads. The encapsulation layer covers the first RDL and has outer surface. The vertical interposers are disposed in the encapsulation layer to electrically connect with the first RDL. The second RDL is formed on the outer surface to electrically connect with the vertical interposers. The carrier includes terminal holes and chip-accommodating hole. The terminal holes correspondingly expose the second pads. The chip-accommodating hole exposes the first pads. The chip is mounted on the encapsulation layer through the chip-accommodating hole to electrically connect with the first pads.

公开(公告)号：US20170278810A1

公开(公告)日：2017-09-28

申请号：US15398845

申请日：2017-01-05

申请人： Amkor Technology, Inc.

发明人： Ronald Patrick Huemoeller ,  Curtis Zwenger ,  David Jon Hiner ,  Corey Reichman

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L21/762 ,  H01L21/48 ,  H01L23/538

CPC分类号： H01L24/03 ,  H01L21/48 ,  H01L21/4853 ,  H01L21/6835 ,  H01L21/76251 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/13082 ,  H01L2224/13101 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

摘要： Methods for an embedded die panel are disclosed and may include fabricating a first layered structure by: forming first redistribution layers on a first carrier, forming a first dielectric layer on the first redistribution layers and carrier, forming a mask pattern on the first dielectric layer exposing a portion of the first dielectric layer, forming a second dielectric layer on the exposed portion of the first dielectric layer, forming vias in the first and second dielectric layers, and forming second redistribution layers on the second dielectric layer. The mask pattern may be removed forming a die cavity defined by the second dielectric layer. A second layered structure coupled to the first layered structure may be formed comprising a second carrier, a third dielectric layer, third and fourth redistribution layers on opposite surfaces of the third dielectric layer, and a semiconductor die.

公开(公告)号：US09685423B2

公开(公告)日：2017-06-20

申请号：US14763898

申请日：2014-01-22

申请人： Pac Tech—Packaging Technologies GmbH

发明人： Ghassem Azdasht

IPC分类号： H01L25/065 ,  H01L25/00 ,  B23K1/00 ,  B23K1/005 ,  H01L23/00 ,  B23K26/14 ,  H01L23/498 ,  B23K101/42

CPC分类号： H01L25/0655 ,  B23K1/0016 ,  B23K1/0056 ,  B23K26/1462 ,  B23K2101/42 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/16057 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/75252 ,  H01L2224/75263 ,  H01L2224/75745 ,  H01L2224/81121 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2225/06551 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

摘要： The invention relates to a chip arrangement (18) comprising a terminal substrate (12) and a plurality of semiconductor substrates (1) which are arranged on the terminal substrate, in particular chips, wherein terminal faces (5) arranged on a contact surface of the chips (1) are connected to terminal faces on a contact surface (14) of the terminal substrate (12), wherein the chips (1) extend parallel with a lateral edge and transversally with their contact surface to the contact surface of the terminal substrate (12), wherein vias (13) are arranged in the terminal substrate, which connect external contacts (15) arranged on an external contact side to terminal faces formed as internal contacts (14) on the contact surface of the terminal substrate, wherein terminal faces of the chips, which are arranged adjacent to the lateral edge, are connected to the internal contacts of the terminal substrate by way of a re-melted solder material deposit (16). Furthermore, the invention relates to a method for producing a chip arrangement (18).

公开(公告)号：US09559082B2

公开(公告)日：2017-01-31

申请号：US15185004

申请日：2016-06-16

申请人： HangZhou HaiCun Information Technology Co., Ltd.

发明人： Guobiao Zhang

IPC分类号： H01L25/065 ,  G11C13/00 ,  H01L25/18 ,  G11C16/26 ,  G11C16/10 ,  G11C16/08 ,  G11C16/04 ,  G11C5/02 ,  G11C5/04 ,  G11C5/14 ,  G11C8/14 ,  H01L23/00 ,  H01L25/10 ,  G11C29/04

CPC分类号： H01L25/0657 ,  G11C5/02 ,  G11C5/04 ,  G11C5/145 ,  G11C8/14 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C2029/0411 ,  G11C2213/71 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/13101 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

摘要： The present invention discloses a three-dimensional vertical memory (3D-MV). It comprises at least a 3D-array die and at least a peripheral-circuit die. The 3D-array die comprises a plurality of vertical memory strings. The number of interconnect levels in the peripheral-circuit die is more than the number of interconnect levels in the 3D-array die, but substantially less than the number of memory cells on each of the vertical memory strings in the 3D-array die.

摘要翻译： 本发明公开了一种立体垂直存储器（3D-MV）。 它包括至少一个3D阵列管芯和至少一个外围电路管芯。 3D阵列管芯包括多个垂直存储器串。 外围电路管芯中的互连级别的数量大于3D阵列管芯中的互连级别的数量，但是基本上小于3D阵列管芯中的每个垂直存储器串上的存储器单元的数量。

公开(公告)号：US20170022356A1

公开(公告)日：2017-01-26

申请号：US15039231

申请日：2014-11-28

申请人： NAMICS CORPORATION

发明人： Tomoya YAMAZAWA ,  Kazuyuki KOHARA ,  Kodai OKOSHI ,  Nobuyuki ABE

IPC分类号： C08L63/00 ,  C08G59/50 ,  H01L23/29 ,  C08G59/62 ,  H01L23/31 ,  C08G59/24 ,  C08G59/42

CPC分类号： C08L63/00 ,  C08G59/24 ,  C08G59/245 ,  C08G59/40 ,  C08G59/42 ,  C08G59/50 ,  C08G59/5033 ,  C08G59/621 ,  C08K3/36 ,  C08L2203/206 ,  H01L21/563 ,  H01L23/29 ,  H01L23/293 ,  H01L23/295 ,  H01L23/3142 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/131 ,  H01L2224/13101 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/29387 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83102 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2924/00014 ,  H01L2924/01048 ,  H01L2924/00012 ,  H01L2924/014

摘要： An epoxy resin composition includes: (A) epoxy resin; (B) a curing agent; (C) 0.1 to 10 mass % of silica filler with an average particle size of 10 nm or more and 100 nm or less; (D) 47 to 75 mass % of silica filler with an average particle size of 0.3 μm or more and 2 μm or less; and (E) 0.1 to 8 mass % of elastomer, wherein the component (C) and the component (D) are contained by 50.1 to 77 mass % in total.

摘要翻译： 环氧树脂组合物包括：（A）环氧树脂; （B）固化剂; （C）0.1〜10质量％的平均粒径为10nm以上且100nm以下的二氧化硅填料; （D）47〜75质量％的平均粒径为0.3μm以上且2μm以下的二氧化硅填料; 和（E）0.1〜8质量％的弹性体，其中成分（C）和成分（D）总计含有50.1〜77质量％。

公开(公告)号：US09552977B2

公开(公告)日：2017-01-24

申请号：US13709824

申请日：2012-12-10

申请人： Intel Corporation

发明人： Mihir K Roy ,  Mathew J Manusharow

IPC分类号： H01L23/00 ,  H01L21/02 ,  G06F1/16 ,  H01L23/50 ,  H01L23/498

CPC分类号： H01L21/02 ,  G06F1/1658 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/50 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/83815 ,  H01L2924/1461 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00

摘要： Embodiments of systems, devices, and methods to minimize warping of ultrathin IC packaged products are generally described herein. In some embodiments, an apparatus includes an IC mounted on a package substrate, and a capacitive stiffener subassembly mounted on the package substrate. The capacitive stiffener subassembly includes a plurality of capacitive elements electrically connected to contacts of the IC.

摘要翻译： 本文通常描述用于最小化超薄IC封装产品的翘曲的系统，装置和方法的实施例。 在一些实施例中，一种装置包括安装在封装衬底上的IC和安装在封装衬底上的电容强化子组件。 电容式加强件子组件包括电连接到IC的触点的多个电容元件。

公开(公告)号：US20160379923A1

公开(公告)日：2016-12-29

申请号：US15260099

申请日：2016-09-08

申请人： INTEL CORPORATION

发明人： Qinglei ZHANG ,  Stefanie M. LOTZ

IPC分类号： H01L23/498 ,  C23C18/32 ,  H01L21/288 ,  C23C18/42 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L23/49838 ,  C23C18/32 ,  C23C18/42 ,  H01L21/288 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/5381 ,  H01L23/5383 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81125 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US09530739B2

公开(公告)日：2016-12-27

申请号：US14609289

申请日：2015-01-29

申请人： QUALCOMM Incorporated

发明人： Young Kyu Song ,  Kyu-Pyung Hwang

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/552 ,  H01L23/60 ,  H01L25/10

CPC分类号： H01L23/5384 ,  H01L21/768 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/60 ,  H01L24/00 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1047 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A package on package (PoP) device includes a first package and a second package. The first package includes a first package substrate, a die coupled to the first package substrate, an encapsulation layer located on the first package substrate, and an inter package connection coupled to the first package substrate. The inter package connection is located in the encapsulation layer. The inter package connection includes a first interconnect configured to provide a first electrical path for a reference ground signal, and a second set of interconnects configured to provide at least one second electrical path for at least one second signal. The first interconnect has a length that is at least about twice as long as a width of the first interconnect. The second set of interconnects is configured to at least be partially coupled to the first interconnect by an electric field.

摘要翻译： 包装（PoP）装置包括第一包装和第二包装。 第一封装包括第一封装衬底，耦合到第一封装衬底的管芯，位于第一封装衬底上的封装层以及耦合到第一封装衬底的封装间连接。 封装间连接位于封装层中。 所述间隔间连接包括被配置为提供用于参考接地信号的第一电路径的第一互连和被配置为为至少一个第二信号提供至少一个第二电路径的第二组互连。 第一互连的长度至少是第一互连宽度的两倍。 第二组互连被配置为通过电场至少部分地耦合到第一互连。

公开(公告)号：US20160372448A1

公开(公告)日：2016-12-22

申请号：US15164866

申请日：2016-05-25

申请人： BroadPak Corporation

发明人： Farhang YAZDANI

IPC分类号： H01L25/10

CPC分类号： H01L25/105 ,  H01L21/486 ,  H01L21/52 ,  H01L23/04 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/467 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/573 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/13147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1082 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/014

摘要： An integrated circuit package is disclosed. The integrated circuit package includes a semiconductor substrate and a TSV-less semiconductor interposer integrated on a substrate. The TSV-less semiconductor interposer has at least one semiconductor device assembled thereon, and the semiconductor devices are coupled to one another using redistribution layers. Wirebonding is used to electrically couple the TSV-less semiconductor interposer to the semiconductor substrate. Combination of Wirebonding, caveties, standoff-substrate and larger BGA balls are used to stacke assemblies.

摘要翻译： 公开了一种集成电路封装。 集成电路封装包括集成在衬底上的半导体衬底和无TSV的半导体插入器。 无TSV的半导体插入器具有组装在其上的至少一个半导体器件，并且半导体器件使用再分布层彼此耦合。 引线键合用于将无TSV的半导体插入件电耦合到半导体衬底。 使用Wirebonding，caveties，standoff-substrate和较大的BGA球的组合来堆叠组件。