公开(公告)号：US12074198B2

公开(公告)日：2024-08-27

申请号：US17453300

申请日：2021-11-02

申请人： Analog Power Conversion LLC

发明人： Amaury Gendron-Hansen ,  Dumitru Gheorge Sdrulla ,  Leslie Louis Szepesi

IPC分类号： H01L29/06 ,  G06F30/39 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  G06F119/08 ,  H01L29/16

CPC分类号： H01L29/0696 ,  G06F30/39 ,  H01L29/0856 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7802 ,  G06F2119/08 ,  H01L29/1608

摘要： A tub of a semiconductor device includes a cool zone with a first projected operating temperature and a hot zone with a second projected operating temperature greater than the first projected operating temperature. A design parameter has a first value in the cool zone and a second value different from the first value in the hot zone. The difference configures the tub to dissipate less heat in the hot zone during operation of the semiconductor device than would be dissipated if the first and second values were equal. The design parameter may be, for example, a tub width, a source structure width, a JFET region width, a channel length, a channel width, a length of a gate, a displacement of a center of the gate relative to a center of a JFET region, a dopant concentration, or a combination thereof.

公开(公告)号：US20240222504A1

公开(公告)日：2024-07-04

申请号：US18533355

申请日：2023-12-08

申请人： Qorvo US, Inc.

发明人： Anup Bhalla ,  Leonid Fursin

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7832 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66893

摘要： Vertical junction field-effect transistors (VJFETs) with integrated source-drain anti-parallel diodes are described. In an embodiment, a trench VJFET with integrated source-drain anti-parallel diodes structure is coupled with a low-voltage metal oxide semiconductor field-effect transistor (MOSFET) in a dual gate cascode configuration.

公开(公告)号：US12015056B2

公开(公告)日：2024-06-18

申请号：US18306359

申请日：2023-04-25

申请人： International Business Machines Corporation

发明人： Yulong Li ,  Paul M. Solomon ,  Siyuranga Koswatta

IPC分类号： H01L29/10 ,  H01L21/28 ,  H01L29/06 ,  H01L29/165 ,  H01L29/205 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/68 ,  H01L29/78 ,  H01L29/788 ,  H01L29/80 ,  H10B12/00 ,  H10B41/30 ,  H10B51/30 ,  H10B63/00

CPC分类号： H01L29/1045 ,  H01L29/0646 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/205 ,  H01L29/40111 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/4983 ,  H01L29/516 ,  H01L29/66431 ,  H01L29/66659 ,  H01L29/66977 ,  H01L29/685 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/802 ,  H10B12/30 ,  H10B41/30 ,  H10B51/30 ,  H10B63/00 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/788

摘要： A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

公开(公告)号：US11984505B2

公开(公告)日：2024-05-14

申请号：US17310762

申请日：2021-03-08

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： ChihCheng Liu

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L29/0607 ,  H01L29/1045 ,  H01L29/4236

摘要： A semiconductor device includes a substrate, a gate oxide layer, a gate electrode and an injection region. The substrate includes a trench, a source region, a drain region and a channel region. The trench includes trench sidewalls and a trench bottom wall. The gate oxide layer is disposed in the trench. The gate oxide layer includes a groove. The gate electrode is disposed in the groove. The injection region is located on at least a side of the trench bottom wall, and at least a part of the injection region is closer to the drain region than the source region so that a threshold voltage at a portion of the channel region close to the injection region is less than a threshold voltage at a portion of the channel region far from the injection region.

公开(公告)号：US20240047530A1

公开(公告)日：2024-02-08

申请号：US18077760

申请日：2022-12-08

申请人： HYUNDAI MOTOR COMPANY ,  KIA CORPORATION

发明人： Jong Seok Lee

IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC分类号： H01L29/1045 ,  H01L29/7806 ,  H01L29/1095 ,  H01L29/086 ,  H01L29/66712

摘要： A power semiconductor device includes a semiconductor layer, a well region located inside the semiconductor layer and having a first conductivity type, a source region located on the well region and having a second conductivity type, a gate region in contact with a side surface of the well region and surrounding the well region, a drift region in contact with bottom surfaces of the well region and the gate region and having the second conductivity type, and a contact region located on the well region and having the first conductivity type. The drift region includes a protruding region in contact with another side surface of the well region. The power semiconductor device includes a source electrode in contact with each of the source region, the contact region, and the protruding region.

公开(公告)号：US11855202B2

公开(公告)日：2023-12-26

申请号：US17028998

申请日：2020-09-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Ching Wu ,  Po-Jen Wang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423

CPC分类号： H01L29/7823 ,  H01L27/088 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4232 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/1045

摘要： A MOS transistor includes a substrate, a first region, a second region, a source region, a drain region, an active gate stack, and a dummy gate stack. The substrate has a first conductivity. The first region having the first conductivity is formed in the substrate. The second region having a second conductivity is formed in the substrate and is adjacent to the first region. The source region with the second conductivity is formed in the first region. The drain region with the second conductivity is formed in the second region. The active gate stack is disposed on the first region. The dummy gate stack is disposed on the second region, and the dummy gate stack is electrically coupled to a variable voltage.

公开(公告)号：US20230369408A1

公开(公告)日：2023-11-16

申请号：US18028454

申请日：2020-11-06

申请人： Hitachi Energy Switzerland AG

发明人： Marco BELLINI ,  Jan VOBECKY ,  Lars KNOLL ,  Gianpaolo ROMANO ,  Giovanni ALFIERI

IPC分类号： H01L29/10 ,  H01L29/78

CPC分类号： H01L29/1045 ,  H01L29/7802 ,  H01L29/7813

摘要： A power semiconductor device is provided. In an embodiment, the power semiconductor device comprises a source region, a channel region in the semiconductor body, and a gate electrode at the channel region. The gate electrode is electrically insulated from the semiconductor body. The channel region is of a second conductivity type different from the first conductivity type. The channel region comprises a first dopant having an activation energy of at most 0.15 eV, and a second dopant having an activation energy of at least 0.3 eV.

公开(公告)号：US20230268396A1

公开(公告)日：2023-08-24

申请号：US18306359

申请日：2023-04-25

申请人： International Business Machines Corporation

发明人： Yulong Li ,  Paul M. Solomon ,  Siyuranga Koswatta

IPC分类号： H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/68 ,  H01L29/49 ,  H01L29/205 ,  H01L29/80 ,  H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/165 ,  H01L29/788 ,  H01L29/423 ,  H10B12/00 ,  H10B41/30 ,  H10B51/30 ,  H10B63/00

CPC分类号： H01L29/1045 ,  H01L29/0646 ,  H01L29/66977 ,  H01L29/685 ,  H01L29/4983 ,  H01L29/205 ,  H01L29/1054 ,  H01L29/66431 ,  H01L29/66659 ,  H01L29/802 ,  H01L29/516 ,  H01L29/785 ,  H01L29/40111 ,  H01L29/165 ,  H01L29/40114 ,  H01L29/7881 ,  H01L29/42324 ,  H10B12/30 ,  H10B41/30 ,  H10B51/30 ,  H10B63/00 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/66825 ,  H01L29/788

摘要： A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

公开(公告)号：US20230261099A1

公开(公告)日：2023-08-17

申请号：US18005058

申请日：2021-06-18

申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION

发明人： KAZUKI KISHIDA ,  KATSUHIKO TAKEUCHI

IPC分类号： H01L29/778 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423

CPC分类号： H01L29/7786 ,  H01L29/1045 ,  H01L29/42364 ,  H01L29/66462 ,  H01L29/2003

摘要： A semiconductor device including: a channel layer; a barrier layer; a source electrode and a drain electrode; a gate electrode; a side surface opening region; and a low-Ns region. The channel layer includes a first nitride semiconductor. The barrier layer includes a second nitride semiconductor. The barrier layer is provided on the channel layer. The source electrode and the drain electrode are provided above the barrier layer. The gate electrode is provided above the barrier layer between the source electrode and the drain electrode. The side surface opening region is at least provided on one of side surfaces of the gate electrode between the source electrode or the drain electrode and the gate electrode. The low-Ns region is provided in the channel layer in correspondence with a planar region provided with the gate electrode and the side surface opening region. The low-Ns region has lower carrier density than carrier density of another region of the channel layer.

公开(公告)号：US20230207680A1

公开(公告)日：2023-06-29

申请号：US18170938

申请日：2023-02-17

申请人： FUJI ELECTRIC CO., LTD.

发明人： Hiroyuki FUJISAWA ,  Akimasa KINOSHITA

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/7808 ,  H01L29/0696 ,  H01L29/7813 ,  H01L29/1045 ,  H01L29/1608

摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an insulating film, first electrodes, a second electrode, and trenches. The first semiconductor regions and the second semiconductor regions are periodically disposed apart from one another in a first direction in which the trenches extend in a stripe pattern.