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    SOI device structure for robust isolation
    2.
    发明授权
    SOI device structure for robust isolation 有权

    公开(公告)号：US11855137B2

    公开(公告)日：2023-12-26

    申请号：US17592997

    申请日：2022-02-04

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Lin-Chen Lu ,  Gulbagh Singh ,  Tsung-Han Tsai ,  Po-Jen Wang

    IPC分类号： H01L29/06 ,  H01L21/762 ,  H01L23/66 ,  H01L29/10

    CPC分类号： H01L29/0649 ,  H01L21/76254 ,  H01L23/66 ,  H01L29/1095

    摘要： This disclosure provides for robust isolation across the SOI structure. In contrast to forming a charge trap layer in specific areas on the structure, a charge trap layer may be built across the insulating/substrate interface. The charge trap layer may be an implantation layer formed throughout and below the insulation layer. Devices built on this SOI structure have reduced cross-talk between the devices. Due to the uniform structure, isolation is robust across the structure and not confined to certain areas. Additionally, deep trench implantation is not required to form the structure, eliminating cost. The semiconductor-on-insulator substrate may include an active silicon layer over an oxide layer. The oxide layer may be over a charge trap layer. The charge trap layer may be over a silicon substrate.

    LDMOS TRANSISTOR
    3.
    发明申请
    LDMOS TRANSISTOR 有权

    公开(公告)号：US20210005747A1

    公开(公告)日：2021-01-07

    申请号：US17028998

    申请日：2020-09-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chun-Ching Wu ,  Po-Jen Wang

    IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423

    摘要： A MOS transistor includes a substrate, a first region, a second region, a source region, a drain region, an active gate stack, and a dummy gate stack. The substrate has a first conductivity. The first region having the first conductivity is formed in the substrate. The second region having a second conductivity is formed in the substrate and is adjacent to the first region. The source region with the second conductivity is formed in the first region. The drain region with the second conductivity is formed in the second region. The active gate stack is disposed on the first region. The dummy gate stack is disposed on the second region, and the dummy gate stack is electrically coupled to a variable voltage.

    NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION
    4.
    发明公开
    NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION 审中-公开

    公开(公告)号：US20230387197A1

    公开(公告)日：2023-11-30

    申请号：US18232545

    申请日：2023-08-10

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Lin-Chen Lu ,  Gulbagh Singh ,  Tsung-Han Tsai ,  Po-Jen Wang

    IPC分类号： H01L29/06 ,  H01L21/762

    CPC分类号： H01L29/0649 ,  H01L21/76254 ,  H01L23/66

    摘要： This disclosure provides for robust isolation across the SOI structure. In contrast to forming a charge trap layer in specific areas on the structure, a charge trap layer may be built across the insulating/substrate interface. The charge trap layer may be an implantation layer formed throughout and below the insulation layer. Devices built on this SOI structure have reduced cross-talk between the devices. Due to the uniform structure, isolation is robust across the structure and not confined to certain areas. Additionally, deep trench implantation is not required to form the structure, eliminating cost. The semiconductor-on-insulator substrate may include an active silicon layer over an oxide layer. The oxide layer may be over a charge trap layer. The charge trap layer may be over a silicon substrate.

    NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION
    5.
    发明申请
    NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION 有权

    公开(公告)号：US20220157935A1

    公开(公告)日：2022-05-19

    申请号：US17592997

    申请日：2022-02-04

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Lin-Chen Lu ,  Gulbagh Singh ,  Tsung-Han Tsai ,  Po-Jen Wang

    IPC分类号： H01L29/06 ,  H01L21/762

    摘要： This disclosure provides for robust isolation across the SOI structure. In contrast to forming a charge trap layer in specific areas on the structure, a charge trap layer may be built across the insulating/substrate interface. The charge trap layer may be an implantation layer formed throughout and below the insulation layer. Devices built on this SOI structure have reduced cross-talk between the devices. Due to the uniform structure, isolation is robust across the structure and not confined to certain areas. Additionally, deep trench implantation is not required to form the structure, eliminating cost. The semiconductor-on-insulator substrate may include an active silicon layer over an oxide layer. The oxide layer may be over a charge trap layer. The charge trap layer may be over a silicon substrate.