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公开(公告)号:US20230369408A1
公开(公告)日:2023-11-16
申请号:US18028454
申请日:2020-11-06
发明人: Marco BELLINI , Jan VOBECKY , Lars KNOLL , Gianpaolo ROMANO , Giovanni ALFIERI
CPC分类号: H01L29/1045 , H01L29/7802 , H01L29/7813
摘要: A power semiconductor device is provided. In an embodiment, the power semiconductor device comprises a source region, a channel region in the semiconductor body, and a gate electrode at the channel region. The gate electrode is electrically insulated from the semiconductor body. The channel region is of a second conductivity type different from the first conductivity type. The channel region comprises a first dopant having an activation energy of at most 0.15 eV, and a second dopant having an activation energy of at least 0.3 eV.
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公开(公告)号:US20240021670A1
公开(公告)日:2024-01-18
申请号:US18039907
申请日:2021-11-30
发明人: Marco BELLINI , Lars KNOLL , Gianpaolo ROMANO
IPC分类号: H01L29/06 , H01L29/16 , H01L29/739 , H01L29/78
CPC分类号: H01L29/063 , H01L29/1608 , H01L29/0696 , H01L29/7397 , H01L29/7813
摘要: A power semiconductor device (1) comprising a semiconductor body (2) extending in a vertical direction between a first main surface (21) and a second main surface (22), a trench (4) extending from the first main surface (21) into the semiconductor body (2) in the vertical direction, and an insulated trench gate electrode (3) that is formed on the first main surface (21) and extends into the trench (4) is specified, wherein the trench (4) is subdivided along a main extension direction of the trench (4) in a plurality of segments (41) and the insulated trench gate electrode (3) continuously extends over the plurality of segments (41).
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公开(公告)号:US20240096937A1
公开(公告)日:2024-03-21
申请号:US18039920
申请日:2021-12-01
发明人: Marco BELLINI , Lars KNOLL , Gianpaolo ROMANO , Yulieth ARANGO
CPC分类号: H01L29/0634 , H01L21/046 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7395 , H01L29/7802
摘要: A power semiconductor device and method for production thereof is specified involving an electrode, a base layer of a first conductivity type provided on the electrode, at least one contact layer provided on the base layer, a gate contact provided on the base layer and on the at least one contact layer, an insulation layer between the gate contact and the base layer and between the at least one contact layer and the gate contact, and at least one zone of a second conductivity type within the base layer, wherein the at least one zone is constructed and arranged to shift away a peak electric field generated in the base layer from the insulation layer between the gate contact and the base layer.
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公开(公告)号:US20230411514A1
公开(公告)日:2023-12-21
申请号:US18240304
申请日:2023-08-30
发明人: Gianpaolo ROMANO , Lars KNOLL , Yulieth ARANGO , Stephan WIRTHS , Andrei MIHAILA
IPC分类号: H01L29/78 , H01L29/51 , H01L29/423 , H01L29/16 , H01L29/786
CPC分类号: H01L29/7813 , H01L29/513 , H01L29/42368 , H01L29/1608 , H01L29/7851 , H01L29/78696
摘要: In at least one embodiment, the power semiconductor device 1) involves a semiconductor body (2), at least one source region (21) in the semiconductor body (2), a gate electrode (3) at the semiconductor body (2), a gate insulator (4, 41, 42) between the semiconductor body (2) and the gate electrode (3), and at least one well region (22) at the at least one source region (21) and at the gate insulator (4, 41, 42), wherein the gate insulator (4, 41, 42) has a varying dielectric capacitance, the dielectric capacitance is in each case a quotient of a dielectric constant and of a geometric thickness of the gate insulator (4, 41, 42) at a specific location thereof, and the dielectric capacitance is larger at the at least one well region (22) than in remaining regions of the gate insulator (4, 42).
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