公开(公告)号：US20220367641A1

公开(公告)日：2022-11-17

申请号：US17706801

申请日：2022-03-29

申请人： FUJI ELECTRIC CO., LTD.

发明人： Hiroyuki FUJISAWA ,  Akimasa KINOSHITA

IPC分类号： H01L29/16 ,  H01L29/423 ,  H01L29/739

摘要： A silicon carbide semiconductor device including a silicon carbide semiconductor substrate. The silicon carbide semiconductor substrate has an active region through which a main current flows, and a termination region surrounding a periphery of the active region in a top view of the silicon carbide semiconductor device. In the top view, the active region is of a rectangular shape, which has two first sides in a direction and two second sides in a direction. The two first sides are each of a first length, and the two second sides are each of a second length, the first length being longer than the second length.

公开(公告)号：US20220344475A1

公开(公告)日：2022-10-27

申请号：US17682589

申请日：2022-02-28

申请人： FUJI ELECTRIC CO., LTD.

发明人： Akimasa KINOSHITA

IPC分类号： H01L29/16 ,  H01L29/06

摘要： In an edge termination region, a FLR structure configured by FLRs having a floating potential and surrounding concentrically a periphery of an active region is provided. The FLR structure is divided into at least two FLR segments with a predetermined FLR as a boundary. An n-th interval between an adjacent two of the FLRs is wider than a first interval between a p+-type extension portion and the FLR closest to a chip center (n=2 to total number of the FLRs). The n-th interval between an adjacent two of the FLRs increases in arithmetic progression the closer the adjacent two are to a chip end, the n-th interval increasing in arithmetic progression by a corresponding one of constant increase increments respectively corresponding to the FLR segments; the closer a FLR segment is to the chip end, the wider is the constant increase increment corresponding thereto.

公开(公告)号：US20200295129A1

公开(公告)日：2020-09-17

申请号：US16773276

申请日：2020-01-27

申请人： FUJI ELECTRIC CO., LTD.

发明人： Akimasa KINOSHITA

IPC分类号： H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66

摘要： A semiconductor device includes lower and upper parallel pn structures. The lower parallel pn structure is disposed at a first semiconductor layer and includes lower first columns of a first conductivity type and lower second columns of a second conductivity type, the lower first and second columns each having a stripe shape, extending in a first direction and being disposed repeatedly alternating with one another in a plane parallel to a front surface. The upper parallel pn structure is disposed at the lower parallel pn structure and includes upper first columns of the first conductivity type and upper second columns of the second conductivity type, the upper first and second columns each having a stripe shape, extending in a second direction different than the first direction and disposed repeatedly alternating with one another in a plane parallel to the front surface.

公开(公告)号：US20190288104A1

公开(公告)日：2019-09-19

申请号：US16269344

申请日：2019-02-06

申请人： Fuji Electric Co., Ltd.

发明人： Akimasa KINOSHITA

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/16 ,  H01L29/08 ,  H01L29/66

摘要： Provided are: injection control regions of a second conductivity type provided on a charge transport region of a first conductivity type; main electrode regions of the first conductivity type provided on the injection control regions; insulated gate electrode structures going through the main electrode region and the injection control regions in the depth direction; an injection suppression region going through the main electrode regions and the injection control regions in the depth direction so as to form a pn junction in a path leading to the charge transport region, the injection suppression region including a semiconductor material with a narrower bandgap than a material of the charge transport region; and a contact protection region of the second conductivity type contacting the bottom surface of the injection suppression region.

公开(公告)号：US20190288073A1

公开(公告)日：2019-09-19

申请号：US16254834

申请日：2019-01-23

申请人： FUJI ELECTRIC CO., LTD.

发明人： Keiji OKUMURA ,  Akimasa KINOSHITA

IPC分类号： H01L29/16 ,  H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L29/08

摘要： In a MOS silicon carbide semiconductor device and a silicon carbide semiconductor circuit device equipped with the silicon carbide semiconductor device, a gate leak current that flows when negative voltage with respect to the potential of the source electrode is applied to the gate electrode is limited to less than 2×10−11 A. The negative voltage applied to the gate electrode is limited to −3V or lower relative to the potential of the source electrode.

公开(公告)号：US20170263745A1

公开(公告)日：2017-09-14

申请号：US15412943

申请日：2017-01-23

申请人： FUJI ELECTRIC CO., LTD.

发明人： Akimasa KINOSHITA

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/16

CPC分类号： H01L29/7802 ,  H01L29/1608 ,  H01L29/66068

摘要： A semiconductor device includes: an n+-type drain region made of a wide-bandgap semiconductor material; an n-type epitaxial layer provided on the top surface of the drain region; an n-type first semiconductor region provided at an upper portion of the epitaxial layer and having a higher impurity concentration than the epitaxial layer; an n-type second semiconductor region provided on the first semiconductor region and having a higher impurity concentration than the first semiconductor region; p-type base regions surrounding to include an upper portion in the middle of the second semiconductor region; n-type source regions provided at upper portions of the base regions to form a channel; and a gate electrode which controls a surface potentials of the channels.

公开(公告)号：US20240297248A1

公开(公告)日：2024-09-05

申请号：US18423989

申请日：2024-01-26

申请人： FUJI ELECTRIC CO., LTD.

发明人： Akimasa KINOSHITA

IPC分类号： H01L29/78 ,  H01L21/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66

CPC分类号： H01L29/7811 ,  H01L21/0465 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813

摘要： A silicon carbide semiconductor device includes: a drift layer provided over an active portion and a breakdown voltage structure portion, the active portion has: a p-type base region provided in the drift layer; an n-type main region provided on the upper surface side of the base region; a p-type buried region provided in contact with the base region on the upper surface side of the drift layer; and a p-type base contact region provided in contact with the main region on the upper surface side of the buried region, the breakdown voltage structure portion has: p-type electric field relaxation regions containing SiC provided on the upper surface side of the drift layer, each of the main region and the base contact region containing SiC contains a 3C-structure in at least a part in contact with the main electrode, and the electric field relaxation regions are composed of a 4H-structure.

公开(公告)号：US20200083338A1

公开(公告)日：2020-03-12

申请号：US16555298

申请日：2019-08-29

申请人： FUJI ELECTRIC CO., LTD.

发明人： Akimasa KINOSHITA

IPC分类号： H01L29/423 ,  H01L27/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/43 ,  H01L29/49

摘要： A gate pad includes a first portion disposed in a gate pad region and a second portion continuous with the first portion and disposed in a gate resistance region. The gate pad has a planar shape in which the second portion protrudes from the first portion. A gate polysilicon layer provided on a front surface of a semiconductor substrate via a gate insulating film is disposed between the semiconductor substrate and an interlayer insulating film, has a surface area that is at least equal to a surface area of the gate pad, and faces the gate pad in a depth direction. The gate polysilicon layer has a planar outline similar to that of the gate pad and includes continuous first and second portions, the first portion facing the first portion of the gate pad overall, and a second portion facing the second portion of the gate pad.

公开(公告)号：US20200006494A1

公开(公告)日：2020-01-02

申请号：US16389276

申请日：2019-04-19

申请人： FUJI ELECTRIC CO., LTD.

发明人： Takashi TSUJI ,  Akimasa KINOSHITA

IPC分类号： H01L29/16 ,  H01L21/02 ,  H01L21/04 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

摘要： A silicon carbide semiconductor device, including a semiconductor substrate having first and second epitaxial layers. The second epitaxial layer is formed on a first main surface of the semiconductor substrate, and includes first and second semiconductor regions, selectively provided in a surface layer of the second epitaxial layer respectively in the active region and the border region, and a third semiconductor region. The semiconductor device further includes a trench penetrating the first and third semiconductor regions to reach the first epitaxial layer, a gate electrode provided in the trench via a gate insulating film, a first electrode electrically connected to the first and third semiconductor regions, and a second electrode provided at a second main surface of the semiconductor substrate. The second semiconductor region is separate from the first semiconductor region. A portion of the third semiconductor region is exposed at the first main surface of the semiconductor substrate, between the first and second semiconductor regions.

公开(公告)号：US20190206985A1

公开(公告)日：2019-07-04

申请号：US16294190

申请日：2019-03-06

申请人： FUJI ELECTRIC CO., LTD.

发明人： Masanobu IWAYA ,  Akimasa KINOSHITA ,  Shinsuke HARADA ,  Yasunori TANAKA

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/04 ,  H01L29/10 ,  H01L29/16

CPC分类号： H01L29/063 ,  H01L21/046 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813

摘要： In a first main surface of a silicon carbide semiconductor base, a trench is formed. On a first main surface side of the silicon carbide semiconductor base, an n-type silicon carbide epitaxial layer is deposited. In a surface of the n-type silicon carbide epitaxial layer, an n-type high-concentration region is provided. In the surface of the n-type silicon carbide epitaxial layer, a first p-type base region and a second p+-type base region are selectively provided. The second p+-type base region is formed at the bottom of the trench. A depth of the n-type high-concentration region is deeper than that of the first p-type base region and the second p+-type base region. Thus, by an easy method, the electric field at a gate insulating film at the bottom of the trench is mitigated, enabling the breakdown voltage of the active region to be maintained and the ON resistance to be lowered.