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    RF SiC MOSFET WITH RECESSED GATE DIELECTRIC
    2.
    发明申请
    RF SiC MOSFET WITH RECESSED GATE DIELECTRIC 有权

    公开(公告)号：US20230022394A1

    公开(公告)日：2023-01-26

    申请号：US17385866

    申请日：2021-07-26

    Applicant: Analog Power Conversion LLC

    Inventor： Dumitru Gheorge Sdrulla ,  Amaury Gendron-Hansen

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/16 ,  H01L29/66

    Abstract: A Field Effect Transistor (FET) may include a semiconductor substrate having a first conductivity type, a semiconductor layer of the first conductivity type formed over the substrate, and a pair of doped bodies of a second conductivity type opposite the first conductivity type formed in the semiconductor layer. A trench filled with a trench dielectric is formed within a region between the doped bodies. The FET may be a Vertical Metal-Oxide-Semiconductor FET (VMOSFET) including a gate dielectric disposed over the region between the doped bodies and the trench, and a gate electrode disposed over the gate dielectric, wherein the trench operates to prevent breakdown of the gate dielectric, or the FET may be a Junction FET. The FET may be designed to operate at radio frequencies or under heavy-ion bombardment. The semiconductor substrate and the semiconductor layer may comprise a wide band-gap semiconductor such as silicon carbide.

    Bridged class-D RF amplifier circuit
    4.
    发明授权
    Bridged class-D RF amplifier circuit 有权

    公开(公告)号：US12081177B2

    公开(公告)日：2024-09-03

    申请号：US17475234

    申请日：2021-09-14

    Applicant: Analog Power Conversion LLC ,  Kyosan Electric Manufacturing Co., Ltd.

    Inventor： Sam Seiichiro Ochi ,  Dumitru Gheorge Sdrulla ,  W. Albert Gu ,  Tetsuya Takata ,  Itsuo Yuzurihara ,  Tomohiro Yoneyama ,  Yu Hosoyamada

    IPC: H03F3/217

    CPC classification number: H03F3/217 ,  H03F2200/451

    Abstract: A full-bridge class-D amplifier circuit comprises first through fourth power devices. First conduction terminals of the first and third power devices are coupled to a first power supply voltage, and second conduction terminals of the second and fourth power devices are coupled to a second power supply voltage. A second conduction terminal of the first power device and a first conduction terminal of the second power device are coupled to a first amplifier output. A second conduction terminal of the third power device and a first conduction terminal of the fourth power device are coupled to a second amplifier output. Left and right driver devices respectively disposed adjacent to left and right sides of the first power device have outputs respectively coupled to left and right control terminals respectively disposed on the left and right sides of the first power device.

    RF SiC MOSFET with recessed gate dielectric
    7.
    发明授权
    RF SiC MOSFET with recessed gate dielectric 有权

    公开(公告)号：US11830943B2

    公开(公告)日：2023-11-28

    申请号：US17385866

    申请日：2021-07-26

    Applicant: Analog Power Conversion LLC

    Inventor： Dumitru Gheorge Sdrulla ,  Amaury Gendron-Hansen

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/423

    CPC classification number: H01L29/7813 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66734

    Abstract: A Field Effect Transistor (FET) may include a semiconductor substrate having a first conductivity type, a semiconductor layer of the first conductivity type formed over the substrate, and a pair of doped bodies of a second conductivity type opposite the first conductivity type formed in the semiconductor layer. A trench filled with a trench dielectric is formed within a region between the doped bodies. The FET may be a Vertical Metal-Oxide-Semiconductor FET (VMOSFET) including a gate dielectric disposed over the region between the doped bodies and the trench, and a gate electrode disposed over the gate dielectric, wherein the trench operates to prevent breakdown of the gate dielectric, or the FET may be a Junction FET. The FET may be designed to operate at radio frequencies or under heavy-ion bombardment. The semiconductor substrate and the semiconductor layer may comprise a wide band-gap semiconductor such as silicon carbide.

    TRANSIENT NOISE REDUCTION FILTERING SYSTEM
    8.
    发明申请
    TRANSIENT NOISE REDUCTION FILTERING SYSTEM 有权

    公开(公告)号：US20210075388A1

    公开(公告)日：2021-03-11

    申请号：US17014948

    申请日：2020-09-08

    Applicant: Analog Power Conversion LLC

    Inventor： Sam Seiichiro OCHI

    IPC: H03H1/00 ,  H03H7/42 ,  H01R13/719

    Abstract: A transient noise reduction filter comprises a cable including one or more twisted pairs of conductors and one or more common mode chokes (CMCs). The one or more CMCs a formed from respective pluralities of turns of the cable. Each of the CMCs may be a magnetic CMC wherein the plurality of turns of the cable are wrapped around a magnetic core, or an air-core CMC wherein the plurality of turns of the cable are not wrapped around a magnetic core but are instead disposed around a non-magnetic material (such as air)

    Power device with partitioned active regions
    9.
    发明授权
    Power device with partitioned active regions 有权

    公开(公告)号：US12224343B2

    公开(公告)日：2025-02-11

    申请号：US17374706

    申请日：2021-07-13

    Applicant: Analog Power Conversion LLC

    Inventor： Amaury Gendron-Hansen ,  Dumitru Gheorge Sdrulla ,  Leslie Louis Szepesi

    IPC: H01L29/78 ,  H01L27/088 ,  H01L29/47 ,  H01L29/49 ,  H01L29/786

    Abstract: A semiconductor device includes a substrate, and a plurality of active regions disposed over the substrate. The plurality of active regions have a first total area. One or more inactive regions are also disposed over the substrate. The one or more inactive regions have a second total area. The second total area is greater than or equal to 1.5 times the first total area. The active regions may be formed in an epitaxial layer formed over the substrate. A plurality of cells of an active device may be disposed in the plurality of active regions. The inactive regions may include only structures that do not dissipate substantial power when the semiconductor device is functioning as it is designed to function.

    SIC STATIC INDUCTION TRANSISTOR WITH DOUBLE SIDE COOLING AND METHOD OF MANUFACTURE
    10.
    发明申请
    SIC STATIC INDUCTION TRANSISTOR WITH DOUBLE SIDE COOLING AND METHOD OF MANUFACTURE 有权

    公开(公告)号：US20240371989A1

    公开(公告)日：2024-11-07

    申请号：US18311159

    申请日：2023-05-02

    Applicant: Analog Power Conversion LLC

    Inventor： Dumitru G. SDRULLA ,  Amaury Gendron-Hansen ,  Wang-Chang A. Gu

    IPC: H01L29/772 ,  H01L23/373 ,  H01L23/528 ,  H01L29/16 ,  H01L29/47 ,  H01L29/66

    Abstract: A silicon carbide (SiC) static induction transistor (SIT) includes a source, a gate disposed over the source and receiving a control signal, a drain disposed over the recessed gate and generating an output signal, an epitaxial pattern disposed between the source and the drain and including a protruding portion, and a gate bus electrically coupled to the gate and including carbon. A method of forming an SiC SIT transistor device includes providing a substrate including a source doped with dopants of a first conductivity type, forming an epitaxial pattern including a protruding portion over the source, forming a recessed gate over the source, forming a gate bus over the recessed gate, forming a drain over the gate bus and the epitaxial pattern, and forming a first heatsink over the drain.

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