公开(公告)号：US09607958B2

公开(公告)日：2017-03-28

申请号：US14512614

申请日：2014-10-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13008 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/20101 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

公开(公告)号：US20130249080A1

公开(公告)日：2013-09-26

申请号：US13426561

申请日：2012-03-21

Applicant: Yaojian Lin ,  Pandi Chelvam Marimuthu ,  Kang Chen

Inventor： Yaojian Lin ,  Pandi Chelvam Marimuthu ,  Kang Chen

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L24/14 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13008 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/20101 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

公开(公告)号：US09337124B1

公开(公告)日：2016-05-10

申请号：US14532761

申请日：2014-11-04

Applicant: HRL LABORATORIES LLC

Inventor： Florian G. Herrault ,  Alexandros Margomenos ,  Miroslav Micovic ,  Melanie S. Yajima ,  Eric M. Prophet

IPC: H01L21/00 ,  H01L23/373 ,  H01L23/40 ,  H01L21/48 ,  H01L23/00 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/768

CPC classification number: H01L23/3736 ,  H01L23/373 ,  H01L23/3732 ,  H01L24/83 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/14 ,  H01L2924/20101 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20105 ,  H01L2924/2064

Abstract: A method for forming a wafer level heat spreader includes providing a mesh wafer, the mesh wafer having a plurality of openings and mesh regions between the openings, bonding the mesh wafer to a backside of an integrated circuit (IC) wafer, the IC wafer comprising a plurality of circuits; and electroplating a heat sink material through the plurality of openings and onto to the backside of the IC wafer.

Abstract translation: 一种形成晶片级散热器的方法，包括：提供网眼晶片，所述网眼晶片在所述开口之间具有多个开口和网格区域，将所述网状晶片接合到集成电路（IC）晶片的背面，所述IC晶片包括 多个电路; 以及通过所述多个开口电镀散热材料并且到达所述IC晶片的背面。

公开(公告)号：US08952538B2

公开(公告)日：2015-02-10

申请号：US12975961

申请日：2010-12-22

Applicant: Hirohisa Matsuki

Inventor： Hirohisa Matsuki

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/1162 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/20101 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/2064 ,  H01L2924/00

Abstract: A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.

Abstract translation: 一种半导体器件包括：具有电极焊盘的集成电路; 布置在所述集成电路上的第一绝缘层; 包括多个布线并设置在第一绝缘层上的再分配层，多个布线中的至少一个电连接到电极焊盘; 在所述多个布线的至少一部分上具有开口的第二绝缘层; 金属膜，设置在所述开口和所述第二绝缘层上，并且电耦合到所述多个布线中的至少一个布线; 以及焊料凸块，所述焊料凸块突出地覆盖所述多个布线中的至少一个未电耦合到所述金属膜的布线。

公开(公告)号：US20230371167A1

公开(公告)日：2023-11-16

申请号：US18246933

申请日：2021-10-18

Applicant: CENTRE NATIONAL D'ETUDES SPATIALES ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ,  Institut Polytechnique de Grenoble ,  UNIVERSITE GRENOBLE ALPES ,  Université de Chambéry - Université Savoie Mont Blanc

Inventor： Pascal FEBVRE ,  Ugur YILMAZ

IPC: H05K1/02 ,  H01L23/00 ,  H05K1/14

CPC classification number: H05K1/0206 ,  H01L24/48 ,  H01L24/08 ,  H05K1/144 ,  H05K2201/041 ,  H01L2224/48106 ,  H01L2224/48157 ,  H01L2224/08235 ,  H01L2924/20101

Abstract: The present description concerns a support (108) for an electronic die (110), comprising: a first printed circuit board (300); a first conductive region (310), intended to receive the die, located on a first surface (108i) of the first board; and a second conductive region (320), intended to receive a thermal connector (200), located on a second surface (108s) of the first board, opposite to the first surface, the first region being connected to the second region by at least one through conductive via (330), located vertically in line with the first region.

公开(公告)号：US09673172B2

公开(公告)日：2017-06-06

申请号：US14649154

申请日：2013-11-24

Applicant: ELTA SYSTEMS LTD.

Inventor： Yaniv Maydar ,  Yohai Joseph

IPC: H01L25/065 ,  H01L23/053 ,  H01L23/66 ,  H01L23/498 ,  H01L23/367 ,  H01L23/00 ,  H01L21/48 ,  H01L21/52 ,  H01L21/56 ,  H01L23/14 ,  H01L23/055

CPC classification number: H01L25/0655 ,  H01L21/4817 ,  H01L21/486 ,  H01L21/52 ,  H01L21/56 ,  H01L23/053 ,  H01L23/055 ,  H01L23/147 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/66 ,  H01L24/17 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0652 ,  H01L2223/6605 ,  H01L2223/6627 ,  H01L2223/6644 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20101 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/20755 ,  H01L2224/45099 ,  H01L2924/207

Abstract: An integrated circuit device and a method of fabricating the same are presented. The integrated circuit device (1) includes two or more active components (30a, 30b), possibly fabricated by different semiconductor technologies, and an interposer structure (10) adapted for carrying the two or more active components such that at least one of the active components is carried on a top surface of the interposer structure. The integrated circuit device also includes at least one metal cap (40), furnished on the top surface of the interposer structure and encapsulating at least one of the active components. Some variants of the integrated circuit device of the invention are suited for operation under extreme conditions.

公开(公告)号：US20150214204A1

公开(公告)日：2015-07-30

申请号：US14165769

申请日：2014-01-28

Applicant: Infineon Technologies AG

Inventor： Manfred Schindler

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L23/495

CPC classification number: H01L25/18 ,  H01L21/561 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/32237 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/32503 ,  H01L2224/83005 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83447 ,  H01L2224/8346 ,  H01L2224/8381 ,  H01L2224/83815 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/97 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/20101 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01049 ,  H01L2924/0665 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2224/83

Abstract: A method for fabricating an electronic device includes simultaneously attaching a first and a second semiconductor chip to a carrier using a transfer means, wherein attaching the first semiconductor chip includes a first attaching method and attaching the second semiconductor chip includes a second attaching method different from the first attaching method.

Abstract translation: 一种电子设备的制造方法，其特征在于，使用转印单元将第一和第二半导体芯片同时附着在载体上，其中，安装所述第一半导体芯片包括第一附着方法，并且所述第二半导体芯片的附着包括与 第一连接方法。

公开(公告)号：US09893029B2

公开(公告)日：2018-02-13

申请号：US14587521

申请日：2014-12-31

Applicant: FUJITSU SEMICONDUCTOR LIMITED

Inventor： Hirohisa Matsuki

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/1162 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/20101 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/2064 ,  H01L2924/00

Abstract: A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.

公开(公告)号：US20150303173A1

公开(公告)日：2015-10-22

申请号：US14649154

申请日：2013-11-24

Applicant: ELTA SYSTEMS LTD.

Inventor： Yaniv MAYDAR ,  Yohai JOSEPH

IPC: H01L25/065 ,  H01L23/053 ,  H01L23/00 ,  H01L21/48 ,  H01L21/52 ,  H01L23/66 ,  H01L23/498 ,  H01L23/367

CPC classification number: H01L25/0655 ,  H01L21/4817 ,  H01L21/486 ,  H01L21/52 ,  H01L21/56 ,  H01L23/053 ,  H01L23/055 ,  H01L23/147 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/66 ,  H01L24/17 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0652 ,  H01L2223/6605 ,  H01L2223/6627 ,  H01L2223/6644 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20101 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/20755 ,  H01L2224/45099 ,  H01L2924/207

Abstract: An integrated circuit device and a method of fabricating the same are presented. The integrated circuit device (1) includes two or more active components (30a, 30b), possibly fabricated by different semiconductor technologies, and an interposer structure (10) adapted for carrying the two or more active components such that at least one of the active components is carried on a top surface of the interposer structure. The integrated circuit device also includes at least one metal cap (40), furnished on the top surface of the interposer structure and encapsulating at least one of the active components. Some variants of the integrated circuit device of the invention are suited for operation under extreme conditions.

Abstract translation: 提出了一种集成电路器件及其制造方法。 集成电路器件（1）包括可能由不同半导体技术制造的两个或多个有源部件（30a，30b）和适于承载两个或多个有源部件的插入器结构（10），使得至少一个有源部件 组件被承载在插入器结构的顶表面上。 集成电路装置还包括至少一个金属盖（40），其设置在插入件结构的顶表面上并且封装至少一个有源部件。 本发明的集成电路装置的一些变型适用于极端条件下的操作。

公开(公告)号：US20150118841A1

公开(公告)日：2015-04-30

申请号：US14587521

申请日：2014-12-31

Applicant: FUJITSU SEMICONDUCTOR LIMITED

Inventor： Hirohisa Matsuki

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/1162 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/20101 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/2064 ,  H01L2924/00

Abstract: A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.

Abstract translation: 一种半导体器件包括：具有电极焊盘的集成电路; 布置在所述集成电路上的第一绝缘层; 包括多个布线并设置在第一绝缘层上的再分配层，多个布线中的至少一个电连接到电极焊盘; 在所述多个布线的至少一部分上具有开口的第二绝缘层; 金属膜，设置在所述开口和所述第二绝缘层上，并且电耦合到所述多个布线中的至少一个布线; 以及焊料凸块，所述焊料凸块突出地覆盖所述多个布线中的至少一个未电耦合到所述金属膜的布线。