公开(公告)号：US09099567B2

公开(公告)日：2015-08-04

申请号：US14089744

申请日：2013-11-25

Applicant: Lakshminarayan Viswanathan ,  L. M. Mahalingam ,  David F. Abdo ,  Jaynal A. Molla

Inventor： Lakshminarayan Viswanathan ,  L. M. Mahalingam ,  David F. Abdo ,  Jaynal A. Molla

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/00 ,  H05K1/14 ,  B23K20/02 ,  B23K35/02 ,  B23K20/24 ,  B23K20/16 ,  B23K20/10 ,  B23K20/00

CPC classification number: H01L24/73 ,  B23K20/002 ,  B23K20/023 ,  B23K20/10 ,  B23K20/16 ,  B23K20/24 ,  B23K35/0244 ,  H01L23/3107 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/83 ,  H01L24/95 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/32225 ,  H01L2224/32238 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/75315 ,  H01L2224/75317 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8348 ,  H01L2224/83484 ,  H01L2224/8384 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01322 ,  H01L2924/04541 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/1306 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/15793 ,  H01L2924/181 ,  H05K3/284 ,  H05K2201/09872 ,  H05K2201/2072 ,  H05K2203/1322 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.

Abstract translation: 将半导体管芯附接到衬底的方法的实施例包括使用插入的管芯附着材料将管芯的底表面放置在衬底的顶表面上。 该方法还包括使半导体管芯的顶表面和衬底的顶表面与保形结构接触，该保形结构包括非固体，压力传递材料，并向保形结构施加压力。 压力通过非固体的压力传递材料传递到半导体管芯的顶表面。 该方法还包括在施加压力的同时，将组件暴露于足以使管芯附着材料烧结的温度。 在将管芯置于衬底上之前，可以在衬底的顶表面和/或半导体管芯的底表面上形成导电的机械锁定特征。

公开(公告)号：US20180108626A1

公开(公告)日：2018-04-19

申请号：US15642742

申请日：2017-07-06

Applicant: International Business Machines Corporation

Inventor： Ekta Misra ,  Krishna R. Tunga

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/0215 ,  H01L2224/02166 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/03013 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05191 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05687 ,  H01L2224/05691 ,  H01L2224/05693 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/07025 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/0455 ,  H01L2924/01073 ,  H01L2924/04541 ,  H01L2924/0469 ,  H01L2924/0463 ,  H01L2924/01013 ,  H01L2924/0476 ,  H01L2924/01074 ,  H01L2924/0496 ,  H01L2924/0538 ,  H01L2924/01044 ,  H01L2924/0479 ,  H01L2924/01027 ,  H01L2924/048 ,  H01L2924/01028 ,  H01L2924/01006

Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.

公开(公告)号：US20170158807A1

公开(公告)日：2017-06-08

申请号：US15321628

申请日：2015-07-01

Applicant: DIC CORPORATION

Inventor： Yasuyo YOSHIMOTO ,  Hiroshi KINOSHITA

IPC: C08G59/32 ,  C09J163/00 ,  C08K9/08 ,  C08K3/36 ,  C08K3/22 ,  H01L23/00 ,  C08K7/02 ,  H05K1/02 ,  H05K1/03 ,  H01L23/29 ,  H01L23/373 ,  C08G59/50 ,  C09J11/04

CPC classification number: C08G59/3218 ,  C08G59/245 ,  C08G59/32 ,  C08G59/5073 ,  C08K3/00 ,  C08K3/22 ,  C08K3/36 ,  C08K7/02 ,  C08K9/08 ,  C08K2003/2227 ,  C08K2201/001 ,  C08L63/00 ,  C09J9/00 ,  C09J11/04 ,  C09J163/00 ,  H01L23/295 ,  H01L23/3737 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2924/01006 ,  H01L2924/04541 ,  H01L2924/0463 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/05032 ,  H01L2924/05042 ,  H01L2924/0532 ,  H01L2924/0542 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/186 ,  H05K1/0203 ,  H05K1/0373 ,  H05K2201/0104

Abstract: An epoxy resin composition for electronic material, containing a polyfunctional biphenyl type epoxy resin that is a triglycidyloxybiphenyl or a tetraglycidyloxybiphenyl and at least one of a curing agent and a curing accelerator is provided. Furthermore, the epoxy resin composition for electronic material, further containing a filler, in particular, a thermal conductive filler, is provided. Furthermore, a cured product obtained by curing the epoxy resin composition for electronic material, and an electronic component containing the cured product are provided.

公开(公告)号：US09455326B2

公开(公告)日：2016-09-27

申请号：US14365152

申请日：2012-02-15

Applicant: Akimasa Kinoshita ,  Noriyuki Iwamuro

Inventor： Akimasa Kinoshita ,  Noriyuki Iwamuro

IPC: H01L29/15 ,  H01L29/47 ,  H01L29/872 ,  H01L29/41 ,  H01L29/16 ,  H01L23/00 ,  H01L29/20

CPC classification number: H01L29/47 ,  H01L24/05 ,  H01L24/48 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41 ,  H01L29/475 ,  H01L29/872 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05186 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/04541 ,  H01L2924/0474 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wide bandgap semiconductor device includes a first conductive type high-concentration wide bandgap semiconductor substrate, a first conductive type low-concentration wide bandgap semiconductor deposited film which is formed on the semiconductor substrate, a metal film which is formed on the semiconductor deposited film so that a Schottoky interface region is formed between the metal film and the semiconductor deposited film, and a second conductive type region which is formed in a region of the semiconductor deposited film corresponding to a peripheral portion of the metal film, wherein the Schottoky interface region in the semiconductor deposited film is surrounded by the second conductive type region so that periodic island regions are formed in the Schottoky interface region.

Abstract translation: 宽带隙半导体器件包括第一导电型高浓度宽带隙半导体衬底，形成在半导体衬底上的第一导电型低浓度宽带隙半导体沉积膜，形成在半导体沉积膜上的金属膜， 在金属膜和半导体沉积膜之间形成Schottoky界面区域，以及形成在与金属膜的周边部分相对应的半导体沉积膜的区域中的第二导电类型区域，其中Schottoky界面区域 半导体沉积膜被第二导电类型区域围绕，使得在Schottoky界面区域中形成周期性的岛状区域。

公开(公告)号：US09425161B2

公开(公告)日：2016-08-23

申请号：US14808779

申请日：2015-07-24

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Lakshminarayan Viswanathan ,  L. M. Mahalingam ,  David F. Abdo ,  Jaynal A. Molla

IPC: H01L23/52 ,  H01L23/00 ,  B23K20/02 ,  B23K35/02 ,  B23K20/24 ,  B23K20/16 ,  B23K20/10 ,  B23K20/00 ,  H01L23/31 ,  H05K3/28

CPC classification number: H01L24/73 ,  B23K20/002 ,  B23K20/023 ,  B23K20/10 ,  B23K20/16 ,  B23K20/24 ,  B23K35/0244 ,  H01L23/3107 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/83 ,  H01L24/95 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/32225 ,  H01L2224/32238 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/75315 ,  H01L2224/75317 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8348 ,  H01L2224/83484 ,  H01L2224/8384 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01322 ,  H01L2924/04541 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/1306 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/15793 ,  H01L2924/181 ,  H05K3/284 ,  H05K2201/09872 ,  H05K2201/2072 ,  H05K2203/1322 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.

Abstract translation: 将半导体管芯附接到衬底的方法的实施例包括使用插入的管芯附着材料将管芯的底表面放置在衬底的顶表面上。 该方法还包括使半导体管芯的顶表面和衬底的顶表面与保形结构接触，该保形结构包括非固体，压力传递材料，并向保形结构施加压力。 压力通过非固体的压力传递材料传递到半导体管芯的顶表面。 该方法还包括在施加压力的同时，将组件暴露于足以使管芯附着材料烧结的温度。 在将管芯置于衬底上之前，可以在衬底的顶表面和/或半导体管芯的底表面上形成导电的机械锁定特征。

公开(公告)号：US20150333031A1

公开(公告)日：2015-11-19

申请号：US14808779

申请日：2015-07-24

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： LAKSHMINARAYAN VISWANATHAN ,  L.M. MAHALINGAM ,  DAVID F. ABDO ,  JAYNAL A. MOLLA

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/73 ,  B23K20/002 ,  B23K20/023 ,  B23K20/10 ,  B23K20/16 ,  B23K20/24 ,  B23K35/0244 ,  H01L23/3107 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/83 ,  H01L24/95 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/32225 ,  H01L2224/32238 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/75315 ,  H01L2224/75317 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8348 ,  H01L2224/83484 ,  H01L2224/8384 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01322 ,  H01L2924/04541 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/1306 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/15793 ,  H01L2924/181 ,  H05K3/284 ,  H05K2201/09872 ,  H05K2201/2072 ,  H05K2203/1322 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.

Abstract translation: 将半导体管芯附接到衬底的方法的实施例包括使用插入的管芯附着材料将管芯的底表面放置在衬底的顶表面上。 该方法还包括使半导体管芯的顶表面和衬底的顶表面与保形结构接触，该保形结构包括非固体，压力传递材料，并向保形结构施加压力。 压力通过非固体的压力传递材料传递到半导体管芯的顶表面。 该方法还包括在施加压力的同时，将组件暴露于足以使管芯附着材料烧结的温度。 在将管芯置于衬底上之前，可以在衬底的顶表面和/或半导体管芯的底表面上形成导电的机械锁定特征。

公开(公告)号：US20140327019A1

公开(公告)日：2014-11-06

申请号：US14365152

申请日：2012-02-15

Applicant: Akimasa Kinoshita ,  Noriyuki Iwamuro

Inventor： Akimasa Kinoshita ,  Noriyuki Iwamuro

IPC: H01L29/47 ,  H01L29/872

CPC classification number: H01L29/47 ,  H01L24/05 ,  H01L24/48 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41 ,  H01L29/475 ,  H01L29/872 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05186 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/04541 ,  H01L2924/0474 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wide bandgap semiconductor device includes a first conductive type high-concentration wide bandgap semiconductor substrate, a first conductive type low-concentration wide bandgap semiconductor deposited film which is formed on the semiconductor substrate, a metal film which is formed on the semiconductor deposited film so that a Schottoky interface region is formed between the metal film and the semiconductor deposited film, and a second conductive type region which is formed in a region of the semiconductor deposited film corresponding to a peripheral portion of the metal film, wherein the Schottoky interface region in the semiconductor deposited film is surrounded by the second conductive type region so that periodic island regions are formed in the Schottoky interface region.

Abstract translation: 宽带隙半导体器件包括第一导电型高浓度宽带隙半导体衬底，形成在半导体衬底上的第一导电型低浓度宽带隙半导体沉积膜，形成在半导体沉积膜上的金属膜， 在金属膜和半导体沉积膜之间形成Schottoky界面区域，以及形成在与金属膜的周边部分相对应的半导体沉积膜的区域中的第二导电类型区域，其中Schottoky界面区域 半导体沉积膜被第二导电类型区域围绕，使得在Schottoky界面区域中形成周期性的岛状区域。

公开(公告)号：US11935850B2

公开(公告)日：2024-03-19

申请号：US17537931

申请日：2021-11-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Kuo-Hui Su

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05087 ,  H01L2224/05088 ,  H01L2224/05098 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01044 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04541 ,  H01L2924/0455 ,  H01L2924/0469 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0509

Abstract: The present application discloses a method for fabricating a semiconductor device with slanted conductive layers. The method for fabricating a semiconductor device includes providing a substrate, forming a first insulating layer above the substrate, forming first slanted recesses along the first insulating layer, and forming first slanted conductive layers in the first slanted recesses and a top conductive layer covering the first slanted conductive layers.

公开(公告)号：US09754905B1

公开(公告)日：2017-09-05

申请号：US15292433

申请日：2016-10-13

Applicant: International Business Machines Corporation

Inventor： Ekta Misra ,  Krishna R. Tunga

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/0215 ,  H01L2224/02166 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/03013 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05191 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05687 ,  H01L2224/05691 ,  H01L2224/05693 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/07025 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/0455 ,  H01L2924/01073 ,  H01L2924/04541 ,  H01L2924/0469 ,  H01L2924/0463 ,  H01L2924/01013 ,  H01L2924/0476 ,  H01L2924/01074 ,  H01L2924/0496 ,  H01L2924/0538 ,  H01L2924/01044 ,  H01L2924/0479 ,  H01L2924/01027 ,  H01L2924/048 ,  H01L2924/01028 ,  H01L2924/01006

Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.

公开(公告)号：US20150146399A1

公开(公告)日：2015-05-28

申请号：US14089744

申请日：2013-11-25

Applicant: LAKSHMINARAYAN VISWANATHAN ,  L.M. Mahalingam ,  David F. Abdo ,  Jaynal A. Molla

Inventor： LAKSHMINARAYAN VISWANATHAN ,  L.M. Mahalingam ,  David F. Abdo ,  Jaynal A. Molla

IPC: H01L23/00 ,  B23K20/02 ,  B23K20/00 ,  B23K20/24 ,  B23K20/16 ,  B23K20/10 ,  H05K1/14 ,  B23K35/02

CPC classification number: H01L24/73 ,  B23K20/002 ,  B23K20/023 ,  B23K20/10 ,  B23K20/16 ,  B23K20/24 ,  B23K35/0244 ,  H01L23/3107 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/83 ,  H01L24/95 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/32225 ,  H01L2224/32238 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/75315 ,  H01L2224/75317 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8348 ,  H01L2224/83484 ,  H01L2224/8384 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01322 ,  H01L2924/04541 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/1306 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/15793 ,  H01L2924/181 ,  H05K3/284 ,  H05K2201/09872 ,  H05K2201/2072 ,  H05K2203/1322 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.

Abstract translation: 将半导体管芯附接到衬底的方法的实施例包括使用插入的管芯附着材料将管芯的底表面放置在衬底的顶表面上。 该方法还包括使半导体管芯的顶表面和衬底的顶表面与保形结构接触，该保形结构包括非固体，压力传递材料，并向保形结构施加压力。 压力通过非固体的压力传递材料传递到半导体管芯的顶表面。 该方法还包括在施加压力的同时，将组件暴露于足以使管芯附着材料烧结的温度。 在将管芯置于衬底上之前，可以在衬底的顶表面和/或半导体管芯的底表面上形成导电的机械锁定特征。