-
1.ELECTRONIC DEVICES WITH ATTACHED DIE STRUCTURES AND METHODS OF FORMATION OF SUCH DEVICES 有权
Title translation: 具有连接结构的电子设备和形成此类设备的方法公开(公告)号:US20160365323A1
公开(公告)日:2016-12-15
申请号:US15247393
申请日:2016-08-25
Applicant: Freescale Semiconductor, Inc.
Inventor: Lakshminarayan Viswanathan , Jaynal A. Molla
CPC classification number: H01L24/83 , H01L21/561 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/3114 , H01L23/36 , H01L23/3677 , H01L23/481 , H01L23/4827 , H01L23/49513 , H01L23/66 , H01L24/03 , H01L24/05 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/741 , H01L24/743 , H01L24/92 , H01L24/94 , H01L29/16 , H01L29/2003 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/03002 , H01L2224/03312 , H01L2224/0332 , H01L2224/03436 , H01L2224/0345 , H01L2224/0346 , H01L2224/03505 , H01L2224/04026 , H01L2224/05009 , H01L2224/05018 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05551 , H01L2224/05558 , H01L2224/05559 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/05794 , H01L2224/05839 , H01L2224/05844 , H01L2224/05847 , H01L2224/05855 , H01L2224/05864 , H01L2224/05887 , H01L2224/0589 , H01L2224/05893 , H01L2224/27002 , H01L2224/2731 , H01L2224/27312 , H01L2224/2732 , H01L2224/27436 , H01L2224/27438 , H01L2224/27505 , H01L2224/29006 , H01L2224/29011 , H01L2224/29012 , H01L2224/29015 , H01L2224/29017 , H01L2224/2908 , H01L2224/29082 , H01L2224/29083 , H01L2224/29084 , H01L2224/291 , H01L2224/29101 , H01L2224/29109 , H01L2224/29111 , H01L2224/29113 , H01L2224/29116 , H01L2224/29117 , H01L2224/29118 , H01L2224/2912 , H01L2224/29124 , H01L2224/29138 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29164 , H01L2224/2918 , H01L2224/29184 , H01L2224/2919 , H01L2224/29193 , H01L2224/2929 , H01L2224/29294 , H01L2224/293 , H01L2224/29339 , H01L2224/29344 , H01L2224/29347 , H01L2224/29355 , H01L2224/29364 , H01L2224/29387 , H01L2224/2939 , H01L2224/29393 , H01L2224/29499 , H01L2224/296 , H01L2224/32245 , H01L2224/48247 , H01L2224/73265 , H01L2224/741 , H01L2224/83191 , H01L2224/83193 , H01L2224/83203 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/8346 , H01L2224/83815 , H01L2224/8384 , H01L2224/92 , H01L2224/92247 , H01L2224/94 , H01L2924/00014 , H01L2924/10158 , H01L2924/1016 , H01L2924/10253 , H01L2924/10272 , H01L2924/1033 , H01L2924/1421 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/3512 , H01L2224/27 , H01L2224/11 , H01L2924/0665 , H01L2924/014 , H01L2924/01015 , H01L2924/01048 , H01L2924/01014 , H01L2924/01032 , H01L2924/0105 , H01L2924/01047 , H01L2924/01028 , H01L2924/01027 , H01L2924/01026 , H01L2224/03 , H01L2224/05099 , H01L2924/01006 , H01L2924/04642 , H01L2924/0503 , H01L2924/01005 , H01L2924/00012 , H01L2224/45099 , H01L2221/68304 , H01L21/304 , H01L2224/83 , H01L2924/0781 , H01L2924/00 , H01L2224/034 , H01L2221/68368 , H01L2224/274
Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.
Abstract translation: 电子器件包括具有下表面的半导体管芯,位于半导体管芯的下表面下方的烧结金属层,位于烧结金属层下面的导电层,以及导电层下面的导电基底。
-
公开(公告)号:US09799580B2
公开(公告)日:2017-10-24
申请号:US15079276
申请日:2016-03-24
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor: Li Li , Jaynal A. Molla , Lakshminarayan Viswanathan
IPC: H01L23/34 , H01L23/047 , H01L21/56 , H01L21/52 , H01L21/50 , H01L23/373 , H01L23/00 , H01L21/603 , H01L21/60
CPC classification number: H01L23/047 , H01L21/50 , H01L21/52 , H01L21/566 , H01L23/3157 , H01L23/373 , H01L23/3736 , H01L23/4334 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/75 , H01L24/83 , H01L24/85 , H01L24/92 , H01L2021/60277 , H01L2021/603 , H01L2224/2929 , H01L2224/29339 , H01L2224/29344 , H01L2224/29347 , H01L2224/29355 , H01L2224/29364 , H01L2224/29393 , H01L2224/29399 , H01L2224/32245 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/83191 , H01L2224/83192 , H01L2224/83193 , H01L2224/8384 , H01L2224/85439 , H01L2224/85455 , H01L2224/92247 , H01L2924/16195 , H01L2924/00014 , H01L2924/00012 , H01L2924/01046 , H01L2924/01079 , H01L2924/00
Abstract: A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.
-
公开(公告)号:US09922894B1
公开(公告)日:2018-03-20
申请号:US15269629
申请日:2016-09-19
Applicant: FREESCALE SEMICONDUCTOR INC.
Inventor: Lakshminarayan Viswanathan , Jaynal A. Molla , David Abdo , Mali Mahalingam , Carl D'Acosta
IPC: H01L23/12 , H01L23/66 , H01L23/20 , H01L23/047 , H01L21/48 , H01L23/057 , H01L23/367 , B22F3/10 , B22F1/00 , B23K35/02 , B23K35/30 , H01L23/00
CPC classification number: H01L23/20 , B22F1/0062 , B22F3/10 , B22F5/10 , B22F7/02 , B22F2301/10 , B22F2301/255 , B22F2302/45 , B23K35/025 , B23K35/30 , H01L21/4817 , H01L21/50 , H01L23/04 , H01L23/047 , H01L23/057 , H01L23/10 , H01L23/3675 , H01L24/32 , H01L24/49 , H01L24/73 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48106 , H01L2224/48177 , H01L2224/73265 , H01L2924/01042 , H01L2924/15747 , H01L2924/3511
Abstract: Air cavity packages and methods for producing air cavity packages containing sintered bonded components, multipart window frames, and/or other unique structural features are disclosed. In one embodiment, a method for fabricating an air cavity package includes the step or process of forming a first metal particle-containing precursor layer between a base flange and a window frame positioned over the base flange. A second metal particle-containing precursor layer is further formed between the base flange and a microelectronic device positioned over the base flange. The metal particle-containing precursor layers are sintered substantially concurrently at a maximum processing temperature less than melt point(s) of metal particles within the layers to produce a first sintered bond layer from the first precursor layer joining the window frame to the base flange and to produce a second sintered bond layer from the second precursor layer joining the microelectronic device to the base flange.
-
公开(公告)号:US09875987B2
公开(公告)日:2018-01-23
申请号:US15247393
申请日:2016-08-25
Applicant: Freescale Semiconductor, Inc.
Inventor: Lakshminarayan Viswanathan , Jaynal A. Molla
IPC: H01L23/00 , H01L29/16 , H01L21/48 , H01L29/20 , H01L23/66 , H01L23/48 , H01L21/78 , H01L23/31 , H01L23/36 , H01L23/367 , H01L23/482 , H01L21/683 , H01L23/495 , H01L21/56
CPC classification number: H01L24/83 , H01L21/561 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/3114 , H01L23/36 , H01L23/3677 , H01L23/481 , H01L23/4827 , H01L23/49513 , H01L23/66 , H01L24/03 , H01L24/05 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/741 , H01L24/743 , H01L24/92 , H01L24/94 , H01L29/16 , H01L29/2003 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/03002 , H01L2224/03312 , H01L2224/0332 , H01L2224/03436 , H01L2224/0345 , H01L2224/0346 , H01L2224/03505 , H01L2224/04026 , H01L2224/05009 , H01L2224/05018 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05551 , H01L2224/05558 , H01L2224/05559 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/05794 , H01L2224/05839 , H01L2224/05844 , H01L2224/05847 , H01L2224/05855 , H01L2224/05864 , H01L2224/05887 , H01L2224/0589 , H01L2224/05893 , H01L2224/27002 , H01L2224/2731 , H01L2224/27312 , H01L2224/2732 , H01L2224/27436 , H01L2224/27438 , H01L2224/27505 , H01L2224/29006 , H01L2224/29011 , H01L2224/29012 , H01L2224/29015 , H01L2224/29017 , H01L2224/2908 , H01L2224/29082 , H01L2224/29083 , H01L2224/29084 , H01L2224/291 , H01L2224/29101 , H01L2224/29109 , H01L2224/29111 , H01L2224/29113 , H01L2224/29116 , H01L2224/29117 , H01L2224/29118 , H01L2224/2912 , H01L2224/29124 , H01L2224/29138 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29164 , H01L2224/2918 , H01L2224/29184 , H01L2224/2919 , H01L2224/29193 , H01L2224/2929 , H01L2224/29294 , H01L2224/293 , H01L2224/29339 , H01L2224/29344 , H01L2224/29347 , H01L2224/29355 , H01L2224/29364 , H01L2224/29387 , H01L2224/2939 , H01L2224/29393 , H01L2224/29499 , H01L2224/296 , H01L2224/32245 , H01L2224/48247 , H01L2224/73265 , H01L2224/741 , H01L2224/83191 , H01L2224/83193 , H01L2224/83203 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/8346 , H01L2224/83815 , H01L2224/8384 , H01L2224/92 , H01L2224/92247 , H01L2224/94 , H01L2924/00014 , H01L2924/10158 , H01L2924/1016 , H01L2924/10253 , H01L2924/10272 , H01L2924/1033 , H01L2924/1421 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/3512 , H01L2224/27 , H01L2224/11 , H01L2924/0665 , H01L2924/014 , H01L2924/01015 , H01L2924/01048 , H01L2924/01014 , H01L2924/01032 , H01L2924/0105 , H01L2924/01047 , H01L2924/01028 , H01L2924/01027 , H01L2924/01026 , H01L2224/03 , H01L2224/05099 , H01L2924/01006 , H01L2924/04642 , H01L2924/0503 , H01L2924/01005 , H01L2924/00012 , H01L2224/45099 , H01L2221/68304 , H01L21/304 , H01L2224/83 , H01L2924/0781 , H01L2924/00 , H01L2224/034 , H01L2221/68368 , H01L2224/274
Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.
-
5.Semiconductor device with mechanical lock features between a semiconductor die and a substrate 有权
Title translation: 在半导体管芯和衬底之间具有机械锁定特征的半导体器件公开(公告)号:US09425161B2
公开(公告)日:2016-08-23
申请号:US14808779
申请日:2015-07-24
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor: Lakshminarayan Viswanathan , L. M. Mahalingam , David F. Abdo , Jaynal A. Molla
IPC: H01L23/52 , H01L23/00 , B23K20/02 , B23K35/02 , B23K20/24 , B23K20/16 , B23K20/10 , B23K20/00 , H01L23/31 , H05K3/28
CPC classification number: H01L24/73 , B23K20/002 , B23K20/023 , B23K20/10 , B23K20/16 , B23K20/24 , B23K35/0244 , H01L23/3107 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/75 , H01L24/83 , H01L24/95 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29164 , H01L2224/29339 , H01L2224/29344 , H01L2224/29347 , H01L2224/29355 , H01L2224/29364 , H01L2224/32225 , H01L2224/32238 , H01L2224/32245 , H01L2224/32258 , H01L2224/48091 , H01L2224/48106 , H01L2224/48137 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2224/75315 , H01L2224/75317 , H01L2224/83192 , H01L2224/83203 , H01L2224/83365 , H01L2224/83385 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/8348 , H01L2224/83484 , H01L2224/8384 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01322 , H01L2924/04541 , H01L2924/04642 , H01L2924/0503 , H01L2924/1306 , H01L2924/15724 , H01L2924/15747 , H01L2924/15786 , H01L2924/15793 , H01L2924/181 , H05K3/284 , H05K2201/09872 , H05K2201/2072 , H05K2203/1322 , H01L2924/00 , H01L2224/45099 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/05599
Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.
Abstract translation: 将半导体管芯附接到衬底的方法的实施例包括使用插入的管芯附着材料将管芯的底表面放置在衬底的顶表面上。 该方法还包括使半导体管芯的顶表面和衬底的顶表面与保形结构接触,该保形结构包括非固体,压力传递材料,并向保形结构施加压力。 压力通过非固体的压力传递材料传递到半导体管芯的顶表面。 该方法还包括在施加压力的同时,将组件暴露于足以使管芯附着材料烧结的温度。 在将管芯置于衬底上之前,可以在衬底的顶表面和/或半导体管芯的底表面上形成导电的机械锁定特征。
-
-
-
-