公开(公告)号：US09893027B2

公开(公告)日：2018-02-13

申请号：US15093713

申请日：2016-04-07

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： David F. Abdo ,  Sivanesan A/L Sathiapalan

IPC: H01L21/44 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/27 ,  H01L24/29 ,  H01L24/80 ,  H01L24/83 ,  H01L2224/03019 ,  H01L2224/0312 ,  H01L2224/03462 ,  H01L2224/05547 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05601 ,  H01L2224/05611 ,  H01L2224/2746 ,  H01L2224/27825 ,  H01L2224/29 ,  H01L2224/29007 ,  H01L2224/29023 ,  H01L2224/29036 ,  H01L2224/29144 ,  H01L2224/29562 ,  H01L2224/2957 ,  H01L2224/29644 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/80048 ,  H01L2224/80355 ,  H01L2224/80359 ,  H01L2224/83048 ,  H01L2224/83097 ,  H01L2224/83192 ,  H01L2224/83355 ,  H01L2924/01079 ,  H01L2924/1033 ,  H01L2924/0105 ,  H01L2924/00014

Abstract: A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die.

公开(公告)号：US20170294393A1

公开(公告)日：2017-10-12

申请号：US15093713

申请日：2016-04-07

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： David F. Abdo ,  Sivanesan A/L Sathiapalan

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/27 ,  H01L24/29 ,  H01L24/80 ,  H01L24/83 ,  H01L2224/03019 ,  H01L2224/0312 ,  H01L2224/03462 ,  H01L2224/05547 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05601 ,  H01L2224/05611 ,  H01L2224/2746 ,  H01L2224/27825 ,  H01L2224/29 ,  H01L2224/29007 ,  H01L2224/29023 ,  H01L2224/29036 ,  H01L2224/29144 ,  H01L2224/29562 ,  H01L2224/2957 ,  H01L2224/29644 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/80048 ,  H01L2224/80355 ,  H01L2224/80359 ,  H01L2224/83048 ,  H01L2224/83097 ,  H01L2224/83192 ,  H01L2224/83355 ,  H01L2924/01079 ,  H01L2924/1033 ,  H01L2924/0105 ,  H01L2924/00014

Abstract: A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die.

公开(公告)号：US09787254B2

公开(公告)日：2017-10-10

申请号：US14862944

申请日：2015-09-23

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： David F. Abdo ,  Jeffrey K. Jones

IPC: H01L23/31 ,  H01L23/66 ,  H01L23/367 ,  H01L21/56 ,  H03F1/30 ,  H01L23/00 ,  H01L23/433 ,  H01L23/522 ,  H01L23/36 ,  H01L23/48 ,  H01L23/482 ,  H03F1/02 ,  H03F1/56 ,  H03F3/193 ,  H03F3/195

CPC classification number: H03F1/301 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/66 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L2223/6644 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/3303 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2924/1304 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1815 ,  H03F1/0288 ,  H03F1/565 ,  H03F3/193 ,  H03F3/195 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/447 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Embodiments include packaged semiconductor devices and methods of manufacturing packaged semiconductor devices. A semiconductor die includes a conductive feature coupled to a bottom surface of the die. The conductive feature only partially covers the bottom die surface to define a conductor-less region that spans a portion of the bottom die surface. The die is encapsulated by attaching the encapsulant material to the bottom die surface (e.g., including over the conductor-less region). The encapsulant material includes an opening that exposes the conductive feature. After encapsulating the die, a heatsink is positioned within the opening, and a surface of the heatsink is attached to the conductive feature. Because the heatsink is attached after encapsulating the die, the heatsink sidewalls are not directly bonded to the encapsulant material.

公开(公告)号：US09111984B2

公开(公告)日：2015-08-18

申请号：US14064422

申请日：2013-10-28

Applicant: Freescale Semiconductor, Inc.

Inventor： Audel A. Sanchez ,  David F. Abdo ,  Michael L. Eleff

IPC: B32B38/10 ,  H01L21/683 ,  H01L21/67 ,  B32B43/00

CPC classification number: H01L21/6836 ,  B32B38/10 ,  B32B43/006 ,  H01L21/67132 ,  H01L2221/68327 ,  H01L2221/68386 ,  Y10T156/1132 ,  Y10T156/1944

Abstract: The embodiments described herein provide an apparatus and method for separating dies from adhesive tape. In general, these techniques use applied vacuum and one or more channels in an extractor base surface to progressively peel adhesive tape away from the die. When the adhesive tape has been peeled away from the entire die the die can be removed and packaged. Such a technique can reduce the strain the die and thus may reduce the probability of cracks occurring in the die, and is thus particularly applicable to removing adhesive tape from relatively thin dies.

Abstract translation: 本文所述的实施例提供了用于将模具与胶带分离的装置和方法。 一般来说，这些技术在抽取器基面中使用应用真空和一个或多个通道，从而将胶带逐渐剥离模头。 当胶带已经从整个模具剥离时，模具可以被去除并包装。 这种技术可以减小模头的应变，从而可以降低在模具中发生裂纹的可能性，因此特别适用于从相对薄的模具去除粘合带。

公开(公告)号：US10109594B2

公开(公告)日：2018-10-23

申请号：US15136326

申请日：2016-04-22

Applicant: Freescale Semiconductor, Inc.

Inventor： Lakshminarayan Viswanathan ,  Michael E. Watts ,  David F. Abdo

IPC: H01L23/552 ,  H01L23/057 ,  H01L23/66 ,  H01L21/52 ,  H01L23/053 ,  H01L23/538 ,  H01L23/58 ,  H01L25/065 ,  H01L25/00 ,  H03F1/02 ,  H03F3/195 ,  H03F3/21 ,  H03F3/213 ,  H01L23/00

Abstract: A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate. A cover is affixed to the substrate so as to extend over the semiconductor device. An isolation structure of electrically conductive material is coupled to the cover in between components of the semiconductor device, with the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. In one version, the isolation structure includes a first leg extending from a ground connection along a side wall of the cover to a cross member contiguous with a primary cover wall that extends over the semiconductor device between the components to be isolated electromagnetically.

公开(公告)号：US10075132B2

公开(公告)日：2018-09-11

申请号：US14666999

申请日：2015-03-24

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Jeffrey K. Jones ,  David F. Abdo ,  Basim H. Noori

IPC: H03F1/02 ,  H03F1/56 ,  H03F3/195 ,  H03F3/21 ,  H03F3/213 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/495 ,  H01L23/522 ,  H01L23/00 ,  H01L49/02 ,  H03F3/193

Abstract: An amplifier includes a semiconductor substrate. A first conductive feature partially covers the bottom substrate surface to define a conductor-less region of the bottom substrate surface. A first current conducting terminal of a transistor is electrically coupled to the first conductive feature. Second and third conductive features may be coupled to other regions of the bottom substrate surface. A first filter circuit includes an inductor formed over a portion of the top substrate surface that is directly opposite the conductor-less region. The first filter circuit may be electrically coupled between a second current conducting terminal of the transistor and the second conductive feature. A second filter circuit may be electrically coupled between a control terminal of the transistor and the third conductive feature. Conductive leads may be coupled to the second and third conductive features, or the second and third conductive features may be coupled to a printed circuit board.

公开(公告)号：US09425161B2

公开(公告)日：2016-08-23

申请号：US14808779

申请日：2015-07-24

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Lakshminarayan Viswanathan ,  L. M. Mahalingam ,  David F. Abdo ,  Jaynal A. Molla

IPC: H01L23/52 ,  H01L23/00 ,  B23K20/02 ,  B23K35/02 ,  B23K20/24 ,  B23K20/16 ,  B23K20/10 ,  B23K20/00 ,  H01L23/31 ,  H05K3/28

CPC classification number: H01L24/73 ,  B23K20/002 ,  B23K20/023 ,  B23K20/10 ,  B23K20/16 ,  B23K20/24 ,  B23K35/0244 ,  H01L23/3107 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/83 ,  H01L24/95 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/32225 ,  H01L2224/32238 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/75315 ,  H01L2224/75317 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8348 ,  H01L2224/83484 ,  H01L2224/8384 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01322 ,  H01L2924/04541 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/1306 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/15793 ,  H01L2924/181 ,  H05K3/284 ,  H05K2201/09872 ,  H05K2201/2072 ,  H05K2203/1322 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.

Abstract translation: 将半导体管芯附接到衬底的方法的实施例包括使用插入的管芯附着材料将管芯的底表面放置在衬底的顶表面上。 该方法还包括使半导体管芯的顶表面和衬底的顶表面与保形结构接触，该保形结构包括非固体，压力传递材料，并向保形结构施加压力。 压力通过非固体的压力传递材料传递到半导体管芯的顶表面。 该方法还包括在施加压力的同时，将组件暴露于足以使管芯附着材料烧结的温度。 在将管芯置于衬底上之前，可以在衬底的顶表面和/或半导体管芯的底表面上形成导电的机械锁定特征。

公开(公告)号：US20160240488A1

公开(公告)日：2016-08-18

申请号：US15136326

申请日：2016-04-22

Applicant: Freescale Semiconductor, Inc.

Inventor： Lakshminarayn Viswanathan ,  Michael E. Watts ,  David F. Abdo

IPC: H01L23/552 ,  H01L23/58 ,  H01L23/538 ,  H01L25/00 ,  H03F1/02 ,  H01L23/057 ,  H01L23/66 ,  H03F3/195 ,  H03F3/213 ,  H03F3/21 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/52 ,  H01L23/053 ,  H01L23/057 ,  H01L23/5386 ,  H01L23/585 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2224/04042 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H03F1/0288 ,  H03F3/195 ,  H03F3/211 ,  H03F3/213 ,  H03F2200/222 ,  H03F2200/451 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate. A cover is affixed to the substrate so as to extend over the semiconductor device. An isolation structure of electrically conductive material is coupled to the cover in between components of the semiconductor device, with the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. In one version, the isolation structure includes a first leg extending from a ground connection along a side wall of the cover to a cross member contiguous with a primary cover wall that extends over the semiconductor device between the components to be isolated electromagnetically.