公开(公告)号：US06713877B2

公开(公告)日：2004-03-30

申请号：US10137836

申请日：2002-05-03

Applicant: Atsuo Hirano ,  Yukio Yoshikawa ,  Kiyotaka Teshima ,  Takemasa Yasukawa

Inventor： Atsuo Hirano ,  Yukio Yoshikawa ,  Kiyotaka Teshima ,  Takemasa Yasukawa

IPC: H01L3300

CPC classification number: H01L33/385 ,  H01L23/62 ,  H01L25/167 ,  H01L33/48 ,  H01L2224/05001 ,  H01L2224/0558 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/10253 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05673 ,  H01L2924/01079 ,  H01L2924/013 ,  H01L2224/05655 ,  H01L2924/01047 ,  H01L2224/05657 ,  H01L2224/05623 ,  H01L2224/05672 ,  H01L2224/05613 ,  H01L2224/05683 ,  H01L2224/05681 ,  H01L2224/05181 ,  H01L2224/05171 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/05184 ,  H01L2224/05166 ,  H01L2224/05666 ,  H01L2224/05647 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05169 ,  H01L2224/05111 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05124 ,  H01L2224/05157 ,  H01L2224/05123 ,  H01L2224/05172 ,  H01L2224/05149 ,  H01L2224/05649 ,  H01L2224/05113 ,  H01L2224/05183 ,  H01L2224/05118 ,  H01L2224/05618 ,  H01L2224/0518 ,  H01L2224/0568 ,  H01L2224/05679 ,  H01L2224/05179 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05155

Abstract: In a light-emitting diode, a substantially square flip chip is placed on a substantially square sub-mount at a position and posture which are obtained through superposition of a center point and center axis of the flip chip on a center point and center axis of the sub-mount and subsequent rotation of the flip chip about the center points by approximately 45°. Therefore, triangular exposed regions are formed on the sub-mount, in which two lead electrodes for the flip chip can be formed. As a result, the flip chip can be placed on a lead frame such that the center axis of the flip chip coincides with the center axis of a parabola of the lead frame. Further, the sub-mount is formed of a semiconductor substrate, and a diode for over-voltage protection is formed within the semiconductor substrate. Therefore, breakage of the light-emitting diode due to excessive voltage can be prevented.

Abstract translation: 在发光二极管中，将大致正方形的倒装芯片放置在通过将倒装芯片的中心点和中心轴叠加在中心点和中心轴上的位置和姿势的位置和姿势 倒装芯片的副安装和随后的旋转围绕中心点约45°。 因此，能够形成用于倒装芯片的两个引线电极的子座上形成三角形露出区域。 结果，倒装芯片可以放置在引线框架上，使得倒装芯片的中心轴线与引线框架的抛物线的中心轴线重合。 此外，子安装件由半导体衬底形成，并且在半导体衬底内形成用于过电压保护的二极管。 因此，可以防止由于过电压导致的发光二极管的破损。

公开(公告)号：US20030129822A1

公开(公告)日：2003-07-10

申请号：US10174357

申请日：2002-06-17

Inventor： Jin-Yuan Lee ,  Chien-Kang Chou ,  Shih-Hsiung Lin ,  Hsi-Shan Kuo

IPC: H01L021/44

CPC classification number: H01L25/0657 ,  H01L24/11 ,  H01L24/13 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05684 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11906 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13123 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/013

Abstract: A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive cylinder and a solder block. The conductive cylinder is formed over the bonding pad of the silicon chip and the solder block is attached to the upper end of the conductive cylinder. The solder block has a melting point lower than the conductive cylinder. The solder block can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive cylinders and finally a solder block is attached to the end of each conductive cylinder.

公开(公告)号：US20030011068A1

公开(公告)日：2003-01-16

申请号：US10192800

申请日：2002-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hee Song ,  Il-Heung Choi ,  Jeong-Jin Kim ,  Hae-Jeong Sohn ,  Chung-Woo Lee

IPC: H01L023/34

CPC classification number: H01L24/05 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49575 ,  H01L23/525 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05116 ,  H01L2224/05118 ,  H01L2224/05155 ,  H01L2224/0516 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05669 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48463 ,  H01L2224/48471 ,  H01L2224/49113 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10161 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

公开(公告)号：US20020145205A1

公开(公告)日：2002-10-10

申请号：US10137836

申请日：2002-05-03

Inventor： Atsuo Hirano ,  Yukio Yoshikawa ,  Kiyotaka Teshima ,  Takemasa Yasukawa

IPC: H01L023/48

CPC classification number: H01L33/385 ,  H01L23/62 ,  H01L25/167 ,  H01L33/48 ,  H01L2224/05001 ,  H01L2224/0558 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/10253 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05673 ,  H01L2924/01079 ,  H01L2924/013 ,  H01L2224/05655 ,  H01L2924/01047 ,  H01L2224/05657 ,  H01L2224/05623 ,  H01L2224/05672 ,  H01L2224/05613 ,  H01L2224/05683 ,  H01L2224/05681 ,  H01L2224/05181 ,  H01L2224/05171 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/05184 ,  H01L2224/05166 ,  H01L2224/05666 ,  H01L2224/05647 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05169 ,  H01L2224/05111 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05124 ,  H01L2224/05157 ,  H01L2224/05123 ,  H01L2224/05172 ,  H01L2224/05149 ,  H01L2224/05649 ,  H01L2224/05113 ,  H01L2224/05183 ,  H01L2224/05118 ,  H01L2224/05618 ,  H01L2224/0518 ,  H01L2224/0568 ,  H01L2224/05679 ,  H01L2224/05179 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05155

Abstract: In a light-emitting diode, a substantially square flip chip is placed on a substantially square sub-mount at a position and posture which are obtained through superposition of a center point and center axis of the flip chip on a center point and center axis of the sub-mount and subsequent rotation of the flip chip about the center points by approximately 45null. Therefore, triangular exposed regions are formed on the sub-mount, in which two lead electrodes for the flip chip can be formed. As a result, the flip chip can be placed on a lead frame such that the center axis of the flip chip coincides with the center axis of a parabola of the lead frame. Further, the sub-mount is formed of a semiconductor substrate, and a diode for over-voltage protection is formed within the semiconductor substrate. Therefore, breakage of the light-emitting diode due to excessive voltage can be prevented.

公开(公告)号：US06445011B1

公开(公告)日：2002-09-03

申请号：US09493183

申请日：2000-01-28

Applicant: Atsuo Hirano ,  Yukio Yoshikawa ,  Kiyotaka Teshima ,  Takemasa Yasukawa

Inventor： Atsuo Hirano ,  Yukio Yoshikawa ,  Kiyotaka Teshima ,  Takemasa Yasukawa

IPC: H01L3300

CPC classification number: H01L33/385 ,  H01L23/62 ,  H01L25/167 ,  H01L33/48 ,  H01L2224/05001 ,  H01L2224/0558 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/10253 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05673 ,  H01L2924/01079 ,  H01L2924/013 ,  H01L2224/05655 ,  H01L2924/01047 ,  H01L2224/05657 ,  H01L2224/05623 ,  H01L2224/05672 ,  H01L2224/05613 ,  H01L2224/05683 ,  H01L2224/05681 ,  H01L2224/05181 ,  H01L2224/05171 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/05184 ,  H01L2224/05166 ,  H01L2224/05666 ,  H01L2224/05647 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05169 ,  H01L2224/05111 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05124 ,  H01L2224/05157 ,  H01L2224/05123 ,  H01L2224/05172 ,  H01L2224/05149 ,  H01L2224/05649 ,  H01L2224/05113 ,  H01L2224/05183 ,  H01L2224/05118 ,  H01L2224/05618 ,  H01L2224/0518 ,  H01L2224/0568 ,  H01L2224/05679 ,  H01L2224/05179 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05155

Abstract: In a light-emitting diode, a substantially square flip chip is placed on a substantially square sub-mount at a position and posture which are obtained through superposition of a center point and center axis of the flip chip on a center point and center axis of the sub-mount and subsequent rotation of the flip chip about the center points by approximately 45°. Therefore, triangular exposed regions are formed on the sub-mount, in which two lead electrodes for the flip chip can be formed. As a result, the flip chip can be placed on a lead frame such that the center axis of the flip chip coincides with the center axis of a parabola of the lead frame. Further, the sub-mount is formed of a semiconductor substrate, and a diode for over-voltage protection is formed within the semiconductor substrate. Therefore, breakage of the light-emitting diode due to excessive voltage can be prevented.

Abstract translation: 在发光二极管中，将大致正方形的倒装芯片放置在通过将倒装芯片的中心点和中心轴叠加在中心点和中心轴上的位置和姿势的位置和姿势 倒装芯片的副安装和随后的旋转围绕中心点约45°。 因此，能够形成用于倒装芯片的两个引线电极的子座上形成三角形露出区域。 结果，倒装芯片可以放置在引线框架上，使得倒装芯片的中心轴线与引线框架的抛物线的中心轴线重合。 此外，子安装件由半导体衬底形成，并且在半导体衬底内形成用于过电压保护的二极管。 因此，可以防止由于过电压导致的发光二极管的破损。

公开(公告)号：US20240290677A1

公开(公告)日：2024-08-29

申请号：US18459111

申请日：2023-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuseong PARK ,  Joongwon SHIN ,  Jong-Min LEE ,  Jimin CHOI

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532

CPC classification number: H01L23/3157 ,  H01L21/56 ,  H01L21/76801 ,  H01L23/3192 ,  H01L23/53295 ,  H01L24/13 ,  H01L23/291 ,  H01L24/05 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05669 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13021 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13176 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496

Abstract: A semiconductor device includes an interlayer insulating layer, a first protective insulating layer on the interlayer insulating layer, a second protective insulating layer on the first protective insulating layer, and insulating structures disposed in at least one of the first protective insulating layer or the second protective insulating layer, wherein the insulating structures include a first insulating structure including a first material having a first physical property, and a second insulating structure including a second material having a second physical property, and the first material and the second material include a same material, and the first physical property and the second physical property are different physical properties.

公开(公告)号：US20240153901A1

公开(公告)日：2024-05-09

申请号：US18151714

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Han-Jong Chia ,  Wei-Ming Wang ,  Kuo-Chung Yee ,  Chen Chen ,  Shih-Peng Tai

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L24/13 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05649 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/06505 ,  H01L2224/08123 ,  H01L2224/08147 ,  H01L2224/13147 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2924/04642 ,  H01L2924/0544 ,  H01L2924/059

Abstract: A first and second semiconductor device are bonded together using a bonding contact pad embedded within a bonding dielectric layer of the first semiconductor device and at least one bonding via embedded within a bonding dielectric layer of the second semiconductor device. The bonding contact pad extends a first dimension in a first direction perpendicular to the major surface of the first semiconductor device and a second dimension in a second direction parallel to the plane of the first semiconductor wafer, the second dimension being at least twice the first dimension. The bonding via extends a third dimension in the first direction and a fourth dimension in the second direction, the third dimension being at least twice the first dimension. The bonding contact pad and bonding via may be at least partially embedded in respective bonding dielectric layers in respective topmost dielectric layers of respective stacked interconnect layers.

公开(公告)号：US20240153900A1

公开(公告)日：2024-05-09

申请号：US18053290

申请日：2022-11-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHENG-FU HUANG ,  SHING-YIH SHIH

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/0215 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05663 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/0568 ,  H01L2224/05684 ,  H01L2224/08145 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a dielectric structure, a pad, a conductive structure, and a buffer structure. The dielectric structure is disposed on the substrate. The pad is embedded in the dielectric structure. The conductive structure is disposed on the pad. The buffer structure is disposed on the pad and separates the conductive structure from the dielectric structure. A coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure.

公开(公告)号：US11824047B2

公开(公告)日：2023-11-21

申请号：US17993248

申请日：2022-11-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/3171 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L21/02063 ,  H01L21/02274 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03831 ,  H01L2224/05155 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/80203 ,  H01L2224/83203 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: The present application provides a method for fabricating a semiconductor device including providing a first semiconductor die including a first substrate including a first substrate including a first region and a second region, a plurality of first through substrate vias in the first region, a first circuit layer on the first substrate, and a control circuit on the first region and in the first circuit layer; forming a plurality of through die vias vertically along the first circuit layer and the second region; providing a second semiconductor die including a plurality of second conductive pads substantially coplanar with a top surface of the second semiconductor die; providing a third semiconductor die including a plurality of third conductive pads substantially coplanar with a top surface of the third semiconductor die; flipping the second semiconductor die and bonding the second semiconductor die onto the first circuit layer.

公开(公告)号：US11776923B2

公开(公告)日：2023-10-03

申请号：US17180359

申请日：2021-02-19

Applicant: SONY CORPORATION

Inventor： Masaki Haneda

IPC: H01L21/768 ,  H01L23/00 ,  H01L27/14 ,  H01L25/065 ,  H01L27/146 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L24/08 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0657 ,  H01L27/14 ,  H01L27/1469 ,  H01L27/14634 ,  H01L27/14636 ,  H01L24/03 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03616 ,  H01L2224/05007 ,  H01L2224/0566 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0801 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80009 ,  H01L2224/80097 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/80986 ,  H01L2924/0104 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/05442 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05657 ,  H01L2924/00014 ,  H01L2224/0566 ,  H01L2924/00014 ,  H01L2224/05618 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/80986 ,  H01L2224/80896 ,  H01L2224/8082

Abstract: Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example.