公开(公告)号：US20100207272A1

公开(公告)日：2010-08-19

申请号：US12389103

申请日：2009-02-19

Applicant: Rainer Steiner ,  Jens Pohl ,  Werner Robl ,  Markus Brunnbauer ,  Gottfried Beer

Inventor： Rainer Steiner ,  Jens Pohl ,  Werner Robl ,  Markus Brunnbauer ,  Gottfried Beer

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02351 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05006 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05546 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/00

Abstract: A semiconductor device includes a chip comprising a contact element, a structured dielectric layer over the chip, and a conductive element coupled to the contact element. The conductive element comprises a first portion embedded in the structured dielectric layer, a second portion at least partially spaced apart from the first portion and embedded in the structured dielectric layer, and a third portion contacting a top of the structured dielectric layer and extending at least vertically over the first portion and the second portion.

Abstract translation: 半导体器件包括芯片，其包括接触元件，芯片上方的结构化介电层以及耦合到接触元件的导电元件。 导电元件包括​​嵌入结构化电介质层中的第一部分，与第一部分至少部分间隔开并嵌入结构化介电层的第二部分，以及接触结构化介电层顶部并至少延伸的第三部分 垂直于第一部分和第二部分。

公开(公告)号：US07635643B2

公开(公告)日：2009-12-22

申请号：US11380215

申请日：2006-04-26

Applicant: Timothy H. Daubenspeck ,  Mukta G. Farooq ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Kevin S. Petrarca ,  Wolfgang Sauter

Inventor： Timothy H. Daubenspeck ,  Mukta G. Farooq ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Kevin S. Petrarca ,  Wolfgang Sauter

IPC: H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05546 ,  H01L2224/05556 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/113 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/00015 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method for forming preferably Pb-lead C4 connections or capture pads with ball limiting metallization on an integrated circuit chip by using a damascene process and preferably Cu metallization in the chip and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad is formed in the top insulating layer and it also serves as the final level of metallization in the chip.

Abstract translation: 一种用于在集成电路芯片上形成优选Pb-lead C4连接或具有球限制金属化的捕获焊盘的方法，其通过使用镶嵌工艺并且优选地在芯片中的Cu金属化和用于兼容性的球限制金属化中。 在两个实施例中，捕获垫形成在顶部绝缘层中，并且还用作芯片中金属化的最终级别。

公开(公告)号：US07485564B2

公开(公告)日：2009-02-03

申请号：US11673618

申请日：2007-02-12

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L21/44

CPC classification number: H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/0501 ,  H01L2224/05083 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2224/114 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A system and method for eliminating undercut when forming a C4 solder bump for BLM (Ball Limiting Metallurgy) and improving the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP with a bottom conductive layer of the barrier metal stack removed by etching. The diffusion barrier and C4 solder bump may be formed by electroless plating, in one embodiment, using a maskless technique, or by an electroplating techniques using a patterned mask. This allows the pitch of the C4 solder bumps to be reduced.

Abstract translation: 一种用于在形成用于BLM（限流冶金）的C4焊料凸块并提高C4间距时消除底切的系统和方法。 在该过程中，在金属焊盘层上方沉积阻挡层金属堆叠。 通过CMP对阻挡层金属（例如Cu）的顶层进行图案化，通过蚀刻去除阻挡金属叠层的底部导电层。 扩散阻挡层和C4焊料凸点可以通过化学镀来形成，在一个实施例中，使用无掩模技术，或通过使用图案化掩模的电镀技术形成。 这样可以减少C4焊料凸点的间距。

公开(公告)号：US07381635B2

公开(公告)日：2008-06-03

申请号：US11183647

申请日：2005-07-18

Applicant: Cyril Cabral, Jr. ,  Michael S. Gordon ,  Kenneth P. Rodbell

Inventor： Cyril Cabral, Jr. ,  Michael S. Gordon ,  Kenneth P. Rodbell

IPC: H01L21/44

CPC classification number: H01L23/556 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76838 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05006 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01063 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01092 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.

Abstract translation: 降低集成电路中软错误率的结构和方法。 该结构包括：半导体衬底; 以及从最下布线电平堆叠到最上布线电平的一个或多个布线电平的堆叠，比最上布线电平更靠近半导体基板的最下布线电平; 以及在所述一个或多个布线层的最上布线层的顶表面上的α粒子阻挡层，所述阻挡层包括金属线和介电材料，所述阻挡层具有阻挡层的厚度和体积 阻挡层中的金属线的百分比足以阻止预定百分比的选定能量的α粒子或更少的击穿阻挡层的金属线穿透到一个或多个布线层或衬底的堆叠中。

公开(公告)号：US07332401B2

公开(公告)日：2008-02-19

申请号：US10874226

申请日：2004-06-24

Applicant: John T. Moore ,  Joseph F. Brooks

Inventor： John T. Moore ,  Joseph F. Brooks

IPC: H01L21/20

CPC classification number: H01L24/05 ,  G11C13/0011 ,  G11C2213/79 ,  H01L21/76823 ,  H01L21/76838 ,  H01L21/76867 ,  H01L24/03 ,  H01L45/085 ,  H01L45/124 ,  H01L45/143 ,  H01L45/1658 ,  H01L45/1683 ,  H01L2224/05006 ,  H01L2224/05546 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01028 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3011 ,  Y10S438/957 ,  H01L2924/00

Abstract: An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the dielectric layer and on the exposed portion of the surface of the first layer and a second layer of conductive material is formed on the conductive binding layer. The binding layer can be an oxide and the second layer a conductive material that is diffusible into an oxide. The electrode structure can be annealed to cause conductive material from the second layer to be chemisorbed into the binding layer to improve adhesion between the first and second layers. A programmable cell can be formed by forming a doped glass layer in the electrode structure.

Abstract translation: 电极结构包括第一层导电材料和形成在第一层表面上的电介质层。 在电介质层中形成开口以露出第一层表面的一部分。 在电介质层上和第一层的表面的暴露部分上形成粘合层，并且在导电结合层上形成第二导电材料层。 结合层可以是氧化物，第二层是可扩散到氧化物中的导电材料。 可以将电极结构退火以使来自第二层的导电材料被化学吸附到结合层中，以改善第一和第二层之间的粘附。 可以通过在电极结构中形成掺杂的玻璃层来形成可编程单元。

公开(公告)号：US20070252274A1

公开(公告)日：2007-11-01

申请号：US11380215

申请日：2006-04-26

Applicant: Timothy Daubenspeck ,  Mukta Farooq ,  Jeffrey Gambino ,  Christopher Muzzy ,  Kevin Petrarca ,  Wolfgang Sauter

Inventor： Timothy Daubenspeck ,  Mukta Farooq ,  Jeffrey Gambino ,  Christopher Muzzy ,  Kevin Petrarca ,  Wolfgang Sauter

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05546 ,  H01L2224/05556 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/113 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/00015 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method for forming preferably Pb-lead C4 connections or capture pads with ball limiting metallization on an integrated circuit chip by using a damascene process and preferably Cu metallization in the chip and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad is formed in the top insulating layer and it also serves as the final level of metallization in the chip.

Abstract translation: 一种用于在集成电路芯片上形成优选Pb-lead C4连接或具有球限制金属化的捕获焊盘的方法，其通过使用镶嵌工艺并且优选地在芯片中的Cu金属化和用于兼容性的球限制金属化中。 在两个实施例中，捕获垫形成在顶部绝缘层中，并且还用作芯片中金属化的最终级别。

公开(公告)号：US07288492B2

公开(公告)日：2007-10-30

申请号：US11184695

申请日：2005-07-19

Applicant: Leonard J. Gardecki ,  James R. Palmer ,  Erik M. Probstfield ,  Adolf E. Wirsing

Inventor： Leonard J. Gardecki ,  James R. Palmer ,  Erik M. Probstfield ,  Adolf E. Wirsing

IPC: H01L21/00 ,  C23C16/00

CPC classification number: B23K3/0623 ,  B23K2101/40 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/74 ,  H01L2221/68359 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/11472 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13116 ,  H01L2224/16 ,  H01L2224/742 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/1305 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of forming a semiconductor interconnect including, in the order recited: (a) providing a semiconductor wafer; (b) forming bonding pads in a terminal wiring level on the frontside of the wafer; (c) reducing the thickness of the wafer; (d) forming solder bumps on the bonding pads; and (e) dicing the wafer into bumped semiconductor chips.

Abstract translation: 一种形成半导体互连的方法，包括：（a）提供半导体晶片; （b）在晶片的前侧的端子布线层中形成接合焊盘; （c）减小晶片的厚度; （d）在焊盘上形成焊料凸块; 和（e）将晶片切割成凸起的半导体芯片。

公开(公告)号：US07268074B2

公开(公告)日：2007-09-11

申请号：US10867346

申请日：2004-06-14

Applicant: Eric Yakobson ,  Richard Hurtubise ,  Christian Witt ,  Qingyun Chen

Inventor： Eric Yakobson ,  Richard Hurtubise ,  Christian Witt ,  Qingyun Chen

IPC: H01L21/44

CPC classification number: H01L21/76846 ,  H01L21/288 ,  H01L21/76849 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05006 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15747 ,  H05K3/107 ,  H05K3/244 ,  H05K2203/072 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device, and a method for forming the cap.

Abstract translation: 在用于结合到多层集成电路器件中的电介质层中的金属填充的互连特征上的多层金属帽以及用于形成帽的方法。

公开(公告)号：US20070026631A1

公开(公告)日：2007-02-01

申请号：US11461416

申请日：2006-07-31

Applicant: Mou-Shiung Lin ,  Hsin-Jung Lo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Ke-Hung Chen

Inventor： Mou-Shiung Lin ,  Hsin-Jung Lo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Ke-Hung Chen

IPC: H01L21/76

CPC classification number: H01L24/12 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0345 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05006 ,  H01L2224/05022 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05683 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/11912 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48673 ,  H01L2224/48683 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A circuitry component comprising a semiconductor substrate, a pad over said semiconductor substrate, a tantalum-containing layer on a side wall and a bottom surface of said pad, a passivation layer over said semiconductor substrate, an opening in said passivation layer exposing said pad, a titanium-containing layer over said pad exposed by said opening, and a gold layer over said titanium-containing layer.

Abstract translation: 一种电路部件，包括半导体衬底，所述半导体衬底上的衬垫，在侧壁上的含钽层和所述焊盘的底表面，所述半导体衬底上的钝化层，所述钝化层中的露出所述衬垫的开口， 由所述开口暴露在所述垫上的含钛层，以及在所述含钛层上方的金层。

公开(公告)号：US07091122B2

公开(公告)日：2006-08-15

申请号：US10920387

申请日：2004-08-18

Applicant: Tadashi Iijima

Inventor： Tadashi Iijima

IPC: H01L21/44

CPC classification number: H01L24/05 ,  H01L21/02126 ,  H01L21/3124 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05006 ,  H01L2224/05093 ,  H01L2224/05546 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/05552

Abstract: Disclosed is a semiconductor device comprising a substrate, a first region provided on the substrate and comprising a first insulating portion which includes an insulating film having a relative dielectric constant of at most 3.0 and a conductive portion which is provided in the first insulating portion, a second region provided on the substrate, located adjacent to the first region in a direction parallel to a major surface of the substrate and comprising a second insulating portion which is located adjacent to the first insulating portion in the direction and which includes no insulating film having a relative dielectric constant of at most 3.0, and a pad provided on the second region and electrically connected to the conductive portion.