公开(公告)号：US20050231992A1

公开(公告)日：2005-10-20

申请号：US11151880

申请日：2005-06-13

Applicant: Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Steven Longcor ,  Edmond Ward

Inventor： Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Steven Longcor ,  Edmond Ward

IPC: G11C11/56 ,  G11C13/00 ,  G11C16/02 ,  H01L27/24 ,  G11C5/00

CPC classification number: G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C2213/31

Abstract: A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing logic over multiple layers allows driver sets to be reused.

Abstract translation: 具有多个内存层的可重写内存。 只要存在只有一个选择了两个端子的存储单元，就可以选择使用层叠交叉点结构中的存储单元的两个端子进行选择，以便选择多层导电线。 通过多层共享逻辑可以重新使用驱动程序集。

公开(公告)号：US20050226046A1

公开(公告)日：2005-10-13

申请号：US10999174

申请日：2004-11-30

Applicant: Jin-Yub Lee ,  Sang-Won Hwang

Inventor： Jin-Yub Lee ,  Sang-Won Hwang

IPC: G11C16/02 ,  G06F12/00 ,  G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C11/34 ,  G11C11/409 ,  G11C11/419 ,  G11C16/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/26

CPC classification number: G06F12/0893 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/2245

Abstract: Method and device for reading data from a semiconductor device, where tR is a read operation time, tT is a buffer transfer time, and tH is a host transfer time, where at least two of tR, tT, and tH may be overlapped to reduce a total transfer time.

Abstract translation: 用于从半导体器件读取数据的方法和装置，其中t R是读取操作时间，tT是缓冲器传送时间，tH是主机传送时间，其中tR，tT和tH中的至少两个可以重叠以减少 总转会时间。

公开(公告)号：US20050226033A1

公开(公告)日：2005-10-13

申请号：US10522316

申请日：2003-07-22

Applicant: Katsutoshi Moriyama ,  Hironobu Mori ,  Nobumichi Okazaki

Inventor： Katsutoshi Moriyama ,  Hironobu Mori ,  Nobumichi Okazaki

IPC: G11C11/41 ,  G11C11/00 ,  G11C11/14 ,  G11C14/00 ,  G11C16/02

CPC classification number: G11C14/0081 ,  G11C11/005 ,  G11C11/14

Abstract: An object of the present invention is to provide a compound storage circuit that includes a storage circuit including a volatile storage circuit and a nonvolatile storage circuit connected in parallel to each other and that is arranged to be capable of an instant-on function by storing information equal to storage information stored in the volatile storage circuit into the nonvolatile storage circuit, the compound storage circuit being capable of reducing power consumption, and a semiconductor device including the compound storage circuit. According to the present invention, in a compound storage circuit including a volatile storage circuit and a nonvolatile storage circuit connected in parallel to each other and a semiconductor device including the compound storage circuit, a determination circuit for comparing first storage information stored in the volatile storage circuit with second storage information that has already been stored in the nonvolatile storage circuit when storage information stored in the volatile storage circuit is written into the nonvolatile storage circuit is provided, and the first storage information is written into the nonvolatile storage circuit only when the first storage information is not equal to the second storage information.

Abstract translation: 本发明的目的是提供一种复合存储电路，它包括一个存储电路，该存储电路包括一个彼此并联连接的易失性存储电路和一个非易失性存储电路，它被设置为能够通过存储信息 等于存储在易失性存储电路中的存储信息到非易失性存储电路中，复合存储电路能够降低功耗，以及包括复合存储电路的半导体器件。 根据本发明，在包括彼此并联连接的易失性存储电路和非易失性存储电路的复合存储电路和包括复合存储电路的半导体器件中，确定电路用于比较存储在易失性存储器 提供了当存储在易失性存储电路中的存储信息被写入非易失性存储电路时已经存储在非易失性存储电路中的具有第二存储信息的电路，并且仅当第一存储信息被写入非易失性存储电路时， 存储信息不等于第二存储信息。

公开(公告)号：US20050226029A1

公开(公告)日：2005-10-13

申请号：US11125350

申请日：2005-05-09

Applicant: Michael Kozicki

Inventor： Michael Kozicki

IPC: G11C11/00 ,  G11C11/34 ,  G11C13/02 ,  G11C16/02 ,  H01L45/00

CPC classification number: G11C11/00 ,  B82Y10/00 ,  G02F1/1525 ,  G02F1/155 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/51 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143 ,  H01L45/1658 ,  H01L45/1683

Abstract: A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally include an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying a bias across the electrodes, and thus information may be stored using the structure.

Abstract translation: 公开了一种微电子可编程结构及其结构编程和编程方法。 可编程结构通常包括离子导体和多个电极。 可以通过在电极上施加偏压来改变结构的电性质，因此可以使用该结构存储信息。

公开(公告)号：US06954378B2

公开(公告)日：2005-10-11

申请号：US10938932

申请日：2004-09-09

Applicant: Tomoharu Tanaka

Inventor： Tomoharu Tanaka

IPC: G11C16/02 ,  G11C8/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  H01L31/0328

CPC classification number: G11C16/10

Abstract: A semiconductor integrated circuit device includes an nonvolatile semiconductor memory cell and a write control circuit. The write control circuit supplies first and second pre-programming pulses and staircase programming pulses to the memory cell independently of the write statuses thereof. The second pre-programming pulse is higher than the first pre-programming pulse by a first potential difference. The staircase programming pulses have an initial voltage lower than the second pre-programming pulse and increase the voltage at a rate of a second potential difference per pulse. The second potential difference is smaller than the first potential difference.

Abstract translation: 半导体集成电路器件包括非易失性半导体存储单元和写入控制电路。 写入控制电路独立于其写入状态向存储器单元提供第一和第二预编程脉冲和阶梯编程脉冲。 第二预编程脉冲比第一预编程脉冲高第一电位差。 阶梯编程脉冲具有低于第二预编程脉冲的初始电压，并以每脉冲第二电位差的速率增加电压。 第二电位差小于第一电位差。

公开(公告)号：US06952368B2

公开(公告)日：2005-10-04

申请号：US10861452

申请日：2004-06-07

Applicant: Seiji Miura ,  Kazushige Ayukawa

Inventor： Seiji Miura ,  Kazushige Ayukawa

IPC: G06F12/16 ,  G06F3/06 ,  G06F12/00 ,  G06F12/06 ,  G11C5/02 ,  G11C8/00 ,  G11C11/00 ,  G11C11/401 ,  G11C11/406 ,  G11C11/407 ,  G11C11/412 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/32

CPC classification number: G06F12/0246 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/005 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40607 ,  G11C11/412 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C29/70

Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

Abstract translation: 一种包括大容量非易失性存储器和至少一个随机存取存储器的半导体器件，所述设备的访问时间与每个随机存取存储器的访问时间相匹配。 半导体存储器件包括：具有第一读取时间的非易失性存储器FLASH; 具有比第一读取时间短100倍的第二读取时间的随机存取存储器DRAM; 电路，其包括连接到FLASH和DRAM两者的控制电路，并且能够控制对那些FLASH和DRAM的访问; 以及连接到电路的多个I / O端子。 结果，在访问DRAM之前，将FLASH数据传送到DRAM，从而与FLASH和DRAM之间的访问时间相匹配。 数据根据需要从DRAM写回到FLASH，从而保持FLASH和DRAM之间的数据匹配并存储数据。

公开(公告)号：US20050213363A1

公开(公告)日：2005-09-29

申请号：US11086588

申请日：2005-03-23

Applicant: Hirofumi Oga

Inventor： Hirofumi Oga

IPC: G11C16/02 ,  G11C11/22 ,  G11C16/04 ,  G11C29/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/24 ,  G11C29/50

CPC classification number: G11C29/02 ,  G11C16/04 ,  G11C29/24 ,  G11C29/50 ,  G11C2029/1204

Abstract: In a disturb test of a selected bit line selected from the plurality of bit lines, the first dummy cell corresponding to the selected bit line is selected, data is written by the constant current flowing in the first dummy cell, and a write bit line voltage is simulated which is the voltage generated in the selected bit line when data is written to the memory cell.

Abstract translation: 在从多个位线选择的所选位线的干扰测试中，选择与所选择的位线对应的第一虚拟单元，通过在第一虚设单元中流动的恒定电流写入数据，写入位线电压 被模拟为当数据被写入存储器单元时在所选位线中产生的电压。

公开(公告)号：US20050213361A1

公开(公告)日：2005-09-29

申请号：US11126044

申请日：2005-05-09

Applicant: Geoffrey Gongwer ,  Daniel Guterman

Inventor： Geoffrey Gongwer ,  Daniel Guterman

IPC: G11C16/02 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C17/00

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3454 ,  G11C16/3481 ,  G11C2211/5621

Abstract: Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a data-dependent programming voltage. Further improvement is accomplished by performing the programming operation in multiphase where each successive phase is executed with a finer programming resolution such as employing a programming voltage with a gentler staircase waveform. These features allow rapid and accurate convergence to the target states for the group of memory cells being programmed in parallel, thereby allowing each cell to store several bits of information without sacrificing performance.

Abstract translation: 具有诸如EEPROM和闪存EEPROM的非易失性电荷存储能力的非易失性存储器由并行应用于多个存储器单元的编程系统来编程。 通过使用数据相关的编程电压以最小的编程脉冲将每个单元编程到其目标状态来实现增强的性能。 通过执行多阶段中的编程操作来实现进一步的改进，其中每个连续相以更精细的编程分辨率执行，例如采用具有较温和的阶梯波形的编程电压。 这些特征允许对并行编程的存储器单元组的目标状态进行快速和准确的收敛，从而允许每个单元存储几位信息而不牺牲性能。

公开(公告)号：US06950349B2

公开(公告)日：2005-09-27

申请号：US10600767

申请日：2003-06-23

Applicant: Tomohiro Nakayama

Inventor： Tomohiro Nakayama

IPC: G11C16/02 ,  G11C16/10 ,  G11C7/00

CPC classification number: G11C16/102

Abstract: A nonvolatile semiconductor memory is provided with a main memory array and a sub-memory array. When rewriting a portion of data having been written in the main memory cell array, a modification data is written into the sub-memory cell array without erasing said main memory cell array. Further, correspondent information on a first address of the main memory cell array storing a data to be modified and a second address of the sub-memory cell array storing the modification data is recorded. At the time of a readout operation, a readout address is compared with the first address recorded in the correspondent information. When said comparison result indicates consistency, a data in the sub-memory cell array of the second address corresponding to the first address is read out. Otherwise, when the comparison result indicates inconsistency, a data in the main memory cell array corresponding to the readout address is read out.

Abstract translation: 非易失性半导体存储器设置有主存储器阵列和子存储器阵列。 当重写已经写入主存储单元阵列的数据的一部分时，将修改数据写入子存储单元阵列而不擦除所述主存储单元阵列。 此外，记录存储要修改的数据的主存储单元阵列的第一地址和存储修改数据的子存储单元阵列的第二地址的对应信息。 在读出操作时，将读出的地址与记录在对应信息中的第一地址进行比较。 当所述比较结果指示一致时，读出与第一地址对应的第二地址的子存储单元阵列中的数据。 否则，当比较结果指示不一致时，读出对应于读出地址的主存储单元阵列中的数据。

公开(公告)号：US20050207259A1

公开(公告)日：2005-09-22

申请号：US11085575

申请日：2005-03-22

Applicant: Kazuyuki Kouno

Inventor： Kazuyuki Kouno

IPC: G11C16/02 ,  G11C7/00 ,  G11C8/00 ,  G11C16/06 ,  G11C16/34 ,  G11C29/36 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C29/36 ,  G11C16/04 ,  G11C16/3454 ,  G11C2029/3602

Abstract: To provide a non-volatile semiconductor memory device which can increase the speed of a writing operation of a physical checker pattern, a logical checker pattern, etc. carried out in an inspection process. First group writing circuits 30a, 30c connected to even-numbered bit lines BL0, BL2 and second group writing circuits 30b, 30d connected to odd-numbered bit lines BL1, BL3 are controlled to an active state and a non-active state respectively on the basis of control signals TSE, TSO. The writing operation of the physical checker pattern is carried out by a program operation for a first page which is carried out while a first word and the first group writing circuits are set to the active state, a program operation for a second page which is carried out while a second word line and the second group writing circuits are set to the active state, and a simultaneous verify operation of the first and second pages which is carried out while the first and second word lines and all the writing circuits are set to the active state.

Abstract translation: 提供一种可以提高在检查过程中执行的物理检查图案，逻辑检查图案等的写入操作的速度的非易失性半导体存储器件。 连接到偶数位线BL 0，BL 2的第一组写入电路30a，连接到奇数位线BL 1，BL 3的第二组写入电路30b，30d被控制为有效状态， 分别基于控制信号TSE，TSO的非有效状态。 物理检查器图案的写入操作通过在第一个字和第一个组写入电路被设置为活动状态的同时执行的第一页的程序操作来执行，该第二页被携带的第二页的程序操作 在第二字线和第二组写入电路被设置为有效状态的同时，在第一和第二字线和所有写入电路被设置为第一和第二页面的同时验证操作中执行第一和第二页面 活跃状态