公开(公告)号：US20050213418A1

公开(公告)日：2005-09-29

申请号：US11087589

申请日：2005-03-24

Applicant: Hirofumi Oga ,  Masahiko Kashimura ,  Masakazu Amanai

Inventor： Hirofumi Oga ,  Masahiko Kashimura ,  Masakazu Amanai

IPC: G11C16/02 ,  G11C8/00 ,  G11C16/04 ,  G11C29/50

CPC classification number: G11C16/0425 ,  G11C16/04 ,  G11C29/50

Abstract: A non-volatile memory device comprises a plurality of bit lines extending in a first direction, a plurality of word lines extending in a second direction substantially perpendicular to the first direction, a plurality of memory cells provided respectively so as to correspond to the positions of the intersections between the plurality of bit lines and the plurality of word lines, a plurality of source lines corresponding to a plurality of memory cells which are connected to a same bit line, a current source capable of supplying the constant current to a selected memory cell and the corresponding bit line and a voltage control circuit which keeps a voltage of a selected bit line equal to or higher than a predetermined voltage.

Abstract translation: 非易失性存储器件包括沿第一方向延伸的多个位线，沿与第一方向大致垂直的第二方向延伸的多条字线，多个存储单元，分别设置成与 所述多个位线和所述多个字线之间的交叉点，对应于连接到同一位线的多个存储器单元的多条源极线，能够向选择的存储单元提供恒定电流的电流源 以及对应的位线和保持所选位线的电压等于或高于预定电压的电压控制电路。

公开(公告)号：US07385856B2

公开(公告)日：2008-06-10

申请号：US11087589

申请日：2005-03-24

Applicant: Hirofumi Oga ,  Masahiko Kashimura ,  Masakazu Amanai

Inventor： Hirofumi Oga ,  Masahiko Kashimura ,  Masakazu Amanai

IPC: G11C16/04

CPC classification number: G11C16/0425 ,  G11C16/04 ,  G11C29/50

Abstract: A non-volatile memory device comprises a plurality of bit lines extending in a first direction, a plurality of word lines extending in a second direction substantially perpendicular to the first direction, a plurality of memory cells provided respectively so as to correspond to the positions of the intersections between the plurality of bit lines and the plurality of word lines, a plurality of source lines corresponding to a plurality of memory cells which are connected to a same bit line, a current source capable of supplying the constant current to a selected memory cell and the corresponding bit line and a voltage control circuit which keeps a voltage of a selected bit line equal to or higher than a predetermined voltage.

Abstract translation: 非易失性存储器件包括沿第一方向延伸的多个位线，沿与第一方向大致垂直的第二方向延伸的多条字线，多个存储单元，分别设置成与 所述多个位线和所述多个字线之间的交叉点，对应于连接到同一位线的多个存储器单元的多条源极线，能够向选择的存储单元提供恒定电流的电流源 以及对应的位线和保持所选位线的电压等于或高于预定电压的电压控制电路。

公开(公告)号：US20050213363A1

公开(公告)日：2005-09-29

申请号：US11086588

申请日：2005-03-23

Applicant: Hirofumi Oga

Inventor： Hirofumi Oga

IPC: G11C16/02 ,  G11C11/22 ,  G11C16/04 ,  G11C29/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/24 ,  G11C29/50

CPC classification number: G11C29/02 ,  G11C16/04 ,  G11C29/24 ,  G11C29/50 ,  G11C2029/1204

Abstract: In a disturb test of a selected bit line selected from the plurality of bit lines, the first dummy cell corresponding to the selected bit line is selected, data is written by the constant current flowing in the first dummy cell, and a write bit line voltage is simulated which is the voltage generated in the selected bit line when data is written to the memory cell.

Abstract translation: 在从多个位线选择的所选位线的干扰测试中，选择与所选择的位线对应的第一虚拟单元，通过在第一虚设单元中流动的恒定电流写入数据，写入位线电压 被模拟为当数据被写入存储器单元时在所选位线中产生的电压。