知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

148 records (took 0.022 seconds)

    Four vertically stacked memory layers in a non-volatile re-writeable memory device
    5.
    发明授权
    Four vertically stacked memory layers in a non-volatile re-writeable memory device 有权
    在非易失性可重写存储器件中的四个垂直堆叠的存储器层

    公开(公告)号：US07847330B2

    公开(公告)日：2010-12-07

    申请号：US12387070

    申请日：2009-04-27

    Applicant: Darrell Rinerson ,  Christophe Chevallier ,  Steve Kuo-Ren Hsia

    Inventor： Darrell Rinerson ,  Christophe Chevallier ,  Steve Kuo-Ren Hsia

    IPC: H01L27/108

    CPC classification number: H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

    Abstract: A multi-layer non-volatile memory integrally formed on top of a substrate including active circuitry is disclosed. Each layer of memory includes memory cells (e.g., a two-terminal memory cell) having a multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a write voltage across the memory cell. Data stored in the memory cells can be non-destructively determined by applying a read voltage across the memory cells. Data storage capacity can be tailored to a specific application by increasing or decreasing the number of memory layers that are integrally fabricated on top of the substrate (e.g., more than four layers or less than four layers). The memory cells can include a non-ohmic device for allowing access to the memory cell only during read and write operations. Each memory layer can comprise a cross point array.

    Abstract translation: 公开了一种整体形成在包括有源电路的基板的顶部上的多层非易失性存储器。 每层存储器包括具有多电阻状态材料层的存储器单元（例如，两端存储单元），其在存储单元上施加写入电压时在低电阻状态和高电阻状态之间改变其电阻状态 。 可以通过在存储器单元上施加读取电压来非存储性地确定存储单元中存储的数据。 数据存储容量可以通过增加或减少在衬底上整体制造的存储层的数量（例如，四层以上或者四层以下）来适应特定应用。 存储器单元可以包括仅在读取和写入操作期间允许访问存储器单元的非欧姆器件。 每个存储器层可以包括交叉点阵列。

    Continuous plane of thin-film materials for a two-terminal cross-point memory
    7.
    发明授权
    Continuous plane of thin-film materials for a two-terminal cross-point memory 失效
    用于两端交叉点存储器的薄膜材料的连续平面

    公开(公告)号：US07742323B2

    公开(公告)日：2010-06-22

    申请号：US11881474

    申请日：2007-07-26

    Applicant: Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Travis Byonghyop Oh

    Inventor： Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Travis Byonghyop Oh

    IPC: G11C11/00

    CPC classification number: H01L27/101 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/165 ,  Y10S257/903

    Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

    Abstract translation: 公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。 薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。 施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。 存储器件可以可选地包括与存储元件和第一和第二包层导体串联电的非欧姆器件。 为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。 存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。 包层导体可以包括由铜制成的芯材料。

Patent Agency Ranking