-
公开(公告)号：US07888711B2
公开(公告)日：2011-02-15
申请号：US12803214
申请日：2010-06-21
IPC分类号： H01L29/66
CPC分类号： H01L27/101 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1641 , H01L45/165 , Y10S257/903
摘要： A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.
-
2.发明授权Continuous plane of thin-film materials for a two-terminal cross-point memory 失效用于两端交叉点存储器的薄膜材料的连续平面公开(公告)号：US07742323B2
公开(公告)日：2010-06-22
申请号：US11881474
申请日：2007-07-26
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1641 , H01L45/165 , Y10S257/903
摘要： A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.
摘要翻译： 公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。 薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。 施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。 存储器件可以可选地包括与存储元件和第一和第二包层导体串联电的非欧姆器件。 为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。 存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。 包层导体可以包括由铜制成的芯材料。
-
3.发明授权Continuous plane of thin-film materials for a two-terminal cross-point memory 有权用于两端交叉点存储器的薄膜材料的连续平面公开(公告)号：US08237142B2
公开(公告)日：2012-08-07
申请号：US12932642
申请日：2011-03-01
CPC分类号： H01L27/101 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1641 , H01L45/165
摘要： A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.
摘要翻译： 公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。 薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。 施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。 存储器件可以可选地包括与存储元件和第一和第二包层导体串联电的非欧姆器件。 为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。 存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。 包层导体可以包括由铜制成的芯材料。
-
公开(公告)号：US20110315948A1
公开(公告)日：2011-12-29
申请号：US13215895
申请日：2011-08-23
申请人： DARRELL RINERSON , JONATHAN BORNSTEIN , DAVID HANSEN , ROBIN CHEUNG , STEVEN W. LONGCOR , RENE MEYER , LAWRENCE SCHLOSS
发明人： DARRELL RINERSON , JONATHAN BORNSTEIN , DAVID HANSEN , ROBIN CHEUNG , STEVEN W. LONGCOR , RENE MEYER , LAWRENCE SCHLOSS
CPC分类号： F01D17/26 , F04D29/563 , H01L21/02565 , H01L27/0688 , H01L27/2409 , H01L27/2418 , H01L27/2472 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1666
摘要： Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).
摘要翻译： 公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOx，LaSrCoOx，LaNiOx等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触并且形成用于将非易失性数据存储为多个的存储元件 （例如，表示存储数据的电阻状态）。
-
公开(公告)号：US20110204019A1
公开(公告)日：2011-08-25
申请号：US12927552
申请日：2010-11-15
IPC分类号： H05K3/00
摘要： Chemical mechanical polishing (CMP) of thin film materials using a slurry including a surfactant chemical operative to polish high portions of the film being planarized while preventing the polishing of low portions of the film is disclosed. The low portions can be in a step reduction region of a deposited film. The CMP process can be used for form a planar surface upon which subsequent thin-film layers can be deposited, such as an electrically conductive material for an electrode. The subsequently deposited thin-film layers are substantially planar as deposited without having to use CMP. The resulting thin-film layers are planar and have a uniform cross-sectional thickness that can be beneficial for layers of memory material for a memory cell. The processing can be performed back-end-of-the-line (BEOL) on a previously front-end-of-the-line (FEOL) processed substrate (e.g., silicon wafer) and the BEOL process can be used to fabricate two-terminal non-volatile cross-point memory arrays.
摘要翻译： 公开了使用包括表面活性剂化学品的浆料的薄膜材料的化学机械抛光（CMP），其可操作以抛光待平坦化的膜的高部分，同时防止薄膜的低部分的抛光。 低部分可以在沉积膜的阶梯还原区域中。 CMP工艺可以用于形成平坦表面，在该平面上可以沉积后续的薄膜层，例如用于电极的导电材料。 随后沉积的薄膜层基本上是平面的，不必使用CMP沉积。 所得到的薄膜层是平面的并且具有均匀的横截面厚度，这对存储单元的记忆材料层是有利的。 可以在先前的前端（FEOL）处理的基板（例如，硅晶片）上执行后端处理（BEOL），并且BEOL过程可用于制造两个 - 终端非易失性交叉点存储器阵列。
-
公开(公告)号：US07832090B1
公开(公告)日：2010-11-16
申请号：US12660424
申请日：2010-02-25
IPC分类号： H01R43/00
CPC分类号： H01L27/24 , H01L21/3212 , H01L21/7684 , H01L21/76849 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165
摘要： Chemical mechanical polishing (CMP) of thin film materials using a slurry including a surfactant chemical operative to polish high portions of the film being planarized while preventing the polishing of low portions of the film is disclosed. The low portions can be in a step reduction region of a deposited film. The CMP process can be used for form a planar surface upon which subsequent thin-film layers can be deposited, such as an electrically conductive material for an electrode. The subsequently deposited thin-film layers are substantially planar as deposited without having to use CMP. The resulting thin-film layers are planar and have a uniform cross-sectional thickness that can be beneficial for layers of memory material for a memory cell. The processing can be performed back-end-of-the-line (BEOL) on a previously front-end-of-the-line (FEOL) processed substrate (e.g., silicon wafer) and the BEOL process can be used to fabricate two-terminal non-volatile cross-point memory arrays.
摘要翻译： 公开了使用包括表面活性剂化学品的浆料的薄膜材料的化学机械抛光（CMP），其可操作以抛光待平坦化的膜的高部分，同时防止薄膜的低部分的抛光。 低部分可以在沉积膜的阶梯还原区域中。 CMP工艺可以用于形成平坦表面，在该平面上可以沉积后续的薄膜层，例如用于电极的导电材料。 随后沉积的薄膜层基本上是平面的，不必使用CMP沉积。 所得到的薄膜层是平面的并且具有均匀的横截面厚度，这对存储单元的记忆材料层是有利的。 可以在先前的前端（FEOL）处理的基板（例如，硅晶片）上执行后端处理（BEOL），并且BEOL过程可用于制造两个 - 终端非易失性交叉点存储器阵列。
-
公开(公告)号：US20100155723A1
公开(公告)日：2010-06-24
申请号：US12653859
申请日：2009-12-18
CPC分类号： H01L45/12 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： Examples of memory stack cladding are described, including a memory stack, comprising a first electrode formed on a substrate, a conductive metal oxide layer deposited on the first electrode, a tunnel barrier layer comprising an insulating metal oxide, the tunnel barrier layer being deposited on the conductive metal oxide layer, a second electrode formed on the tunnel barrier layer, a glue layer deposited on the second electrode, a mask layer deposited on the glue layer, and a cladding layer deposited substantially over one or more surfaces of the memory stack, the cladding layer being configured to provide a barrier to prevent one or more hydrogen ions from diffusing through the one or more surfaces of the memory stack. The memory stack may define a two-terminal non-volatile memory cell operative to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage.
摘要翻译： 描述了存储器堆叠包层的示例，包括存储器堆叠，其包括形成在衬底上的第一电极，沉积在第一电极上的导电金属氧化物层，包括绝缘金属氧化物的隧道势垒层，隧道势垒层沉积在 导电金属氧化物层，形成在隧道势垒层上的第二电极，沉积在第二电极上的胶层，沉积在胶层上的掩模层以及基本上沉积在存储堆的一个或多个表面上的包覆层， 所述包覆层被配置为提供阻挡层以防止一个或多个氢离子通过所述存储器堆叠的所述一个或多个表面扩散。 存储器堆栈可以定义一个双端非易失性存储器单元，其操作以将数据存储为可以通过施加读取电压而非破坏性地确定的多个导电率分布。
-
公开(公告)号：US07618894B2
公开(公告)日：2009-11-17
申请号：US11881475
申请日：2007-07-26
IPC分类号： H01L21/465
CPC分类号： H01L21/32136 , G11C13/0009 , H01L27/101 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： Multi-step selective etching. Etching an unmasked region associated with each layer of a plurality of layers, the plurality of layers comprising a stack, wherein the unmasked region of each of the plurality of layers is etched while exposed to a temperature, a pressure, a vacuum, using a plurality of etchants, wherein at least one of the plurality of etchants comprises an inert gas and oxygen, wherein the etchant oxidizes the at least one layer that can be oxidized such that the etching stops, the plurality of etchants leaving substantially unaffected a masked region associated with each layer of the plurality of layers, wherein two or more of the plurality of layers comprises a memory stack, and preventing corrosion of at least one of the plurality of layers comprising a conductive metal oxide by supplying oxygen to the stack after etching the unmasked region without breaking the vacuum.
摘要翻译： 多步选择性蚀刻。 蚀刻与多个层的每个层相关联的未掩模区域，所述多个层包括堆叠，其中在暴露于温度，压力，真空的情况下，多层中的每一层的未屏蔽区域被蚀刻，使用多个层 的蚀刻剂，其中所述多个蚀刻剂中的至少一个包含惰性气体和氧气，其中所述蚀刻剂氧化所述至少一个可被氧化的层，使得蚀刻停止，所述多个蚀刻剂基本上不影响与 所述多个层中的每个层，其中所述多个层中的两个或更多层包括存储堆叠，并且通过在蚀刻所述未掩模区域之后向所述堆叠提供氧而防止包括导电金属氧化物的所述多个层中的至少一个的腐蚀 不破坏真空。
-
公开(公告)号：US20090029555A1
公开(公告)日：2009-01-29
申请号：US11881475
申请日：2007-07-26
IPC分类号： H01L21/302 , H01L21/311
CPC分类号： H01L21/32136 , G11C13/0009 , H01L27/101 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： Multi-step selective etching. Etching an unmasked region associated with each layer of a plurality of layers, the plurality of layers comprising a stack, wherein the unmasked region of each of the plurality of layers is etched while exposed to a temperature, a pressure, a vacuum, using a plurality of etchants, wherein at least one of the plurality of etchants comprises an inert gas and oxygen, wherein the etchant oxidizes the at least one layer that can be oxidized such that the etching stops, the plurality of etchants leaving substantially unaffected a masked region associated with each layer of the plurality of layers, wherein two or more of the plurality of layers comprises a memory stack, and preventing corrosion of at least one of the plurality of layers comprising a conductive metal oxide by supplying oxygen to the stack after etching the unmasked region without breaking the vacuum.
摘要翻译： 多步选择性蚀刻。 蚀刻与多个层的每个层相关联的未掩模区域，所述多个层包括堆叠，其中在暴露于温度，压力，真空的情况下，多层中的每一层的未屏蔽区域被蚀刻，使用多个层 的蚀刻剂，其中所述多个蚀刻剂中的至少一个包含惰性气体和氧气，其中所述蚀刻剂氧化所述至少一个可被氧化的层，使得蚀刻停止，所述多个蚀刻剂基本上不影响与 所述多个层中的每个层，其中所述多个层中的两个或更多层包括存储堆叠，并且通过在蚀刻所述未掩模区域之后向所述堆叠提供氧而防止包括导电金属氧化物的所述多个层中的至少一个的腐蚀 不破坏真空。
-
10.发明授权公开(公告)号：US08003511B2
公开(公告)日：2011-08-23
申请号：US12653851
申请日：2009-12-18
申请人： Darrell Rinerson , Jonathan Bornstein , Robin Cheung , David Hansen , Steven W. Longcor , Rene Meyer , Lawrence Schloss
发明人： Darrell Rinerson , Jonathan Bornstein , Robin Cheung , David Hansen , Steven W. Longcor , Rene Meyer , Lawrence Schloss
IPC分类号： H01L21/44
CPC分类号： F01D17/26 , F04D29/563 , H01L21/02565 , H01L27/0688 , H01L27/2409 , H01L27/2418 , H01L27/2472 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1666
摘要： Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).
摘要翻译： 公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOX，LaSrCoOX，LaNiOX等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触，并且形成用于将非易失性数据存储为多个的存储元件 （例如，表示存储数据的电阻状态）。
-
-
-
-
-
-
-
-
-
搜索结果
16 条记录 (耗时 0.019 秒)
