公开(公告)号：US08062942B2

公开(公告)日：2011-11-22

申请号：US12215958

申请日：2008-06-30

Applicant: Darrell Rinerson ,  Wayne Kinney ,  Edmond Ward ,  Steve Kuo-Ren Hsia ,  Steven W. Longcor ,  Christophe J. Chevallier ,  John E. Sanchez, Jr. ,  Philip Swab

Inventor： Darrell Rinerson ,  Wayne Kinney ,  Edmond Ward ,  Steve Kuo-Ren Hsia ,  Steven W. Longcor ,  Christophe J. Chevallier ,  John E. Sanchez, Jr. ,  Philip Swab

IPC: H01L21/00

CPC classification number: H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.

Abstract translation: 提供经处理的导电元件。 可以通过在导电元件上沉积反应性金属或非常薄的材料层来处理导电元件。 反应性金属（或非常薄的材料层）通常将夹在导电元件和电极之间。 该结构还具有非线性IV特性，这在某些阵列中是有利的。

公开(公告)号：US20090303772A1

公开(公告)日：2009-12-10

申请号：US12456627

申请日：2009-06-18

Applicant: Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  John E. Sanchez, JR. ,  Lawrence Schloss ,  Philip Swab ,  Edmond Ward

Inventor： Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  John E. Sanchez, JR. ,  Lawrence Schloss ,  Philip Swab ,  Edmond Ward

IPC: G11C11/00 ,  H01L45/00 ,  G11C7/00

CPC classification number: H01L45/08 ,  G06F17/5045 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/005 ,  G11C2013/009 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/54 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625

Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

Abstract translation: 公开了使用混合价态导电氧化物的记忆体。 存储器包括在其缺氧状态下导电性较差的混合价态导电氧化物和作为电解质的氧的混合电子离子导体并且促进有效引起氧离子运动的电场。

公开(公告)号：US07326979B2

公开(公告)日：2008-02-05

申请号：US10665882

申请日：2003-09-19

Applicant: Darrell Rinerson ,  Wayne Kinney ,  John E. Sanchez, Jr. ,  Steven W. Longcor ,  Steve Kuo-Ren Hsia ,  Edmond Ward ,  Christophe Chevallier

Inventor： Darrell Rinerson ,  Wayne Kinney ,  John E. Sanchez, Jr. ,  Steven W. Longcor ,  Steve Kuo-Ren Hsia ,  Edmond Ward ,  Christophe Chevallier

IPC: H01L29/76

CPC classification number: G11C13/003 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/2418 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/165

Abstract: A multi-resistive state element that uses a treated interface is provided. A memory plug includes at least two electrodes that sandwich a multi-resistive state element. Using different treatments on both electrode/multi-resistive state element interfaces improves the memory properties of the entire memory device.

Abstract translation: 提供了使用处理接口的多电阻状态元素。 存储插头包括夹着多电阻状态元件的至少两个电极。 在电极/多电阻状态元件接口上使用不同的处理可改善整个存储器件的存储器特性。

公开(公告)号：US5597458A

公开(公告)日：1997-01-28

申请号：US500296

申请日：1995-07-10

Applicant: John E. Sanchez, Jr. ,  Darin A. Chan ,  Paul R. Besser

Inventor： John E. Sanchez, Jr. ,  Darin A. Chan ,  Paul R. Besser

IPC: C23C14/16 ,  C23C14/54 ,  H01L21/768 ,  C23C14/34

CPC classification number: C23C14/541 ,  C23C14/165 ,  H01L21/76838

Abstract: A method for forming an alloy film by cooling a substrate during a sputter deposition process. In one embodiment, aluminum-copper (Al-Cu) alloy film is deposited on a substrate while the substrate is maintained at a temperature lower than 100.degree. C. during a sputter deposition process, thereby reducing the precipitation of CuAl.sub.2. The substrate is cooled by pumping a coolant gas through a cooled platen and against the substrate during processing. Subsequent film formation prior to etching is also performed below 100.degree. C. to prevent precipitation of CuAl.sub.2 until the Al-Cu alloy film is etched. Large crystal grains are formed by annealing the substrate after etching.

Abstract translation: 一种通过在溅射沉积工艺期间冷却基板来形成合金膜的方法。 在一个实施例中，在溅射沉积工艺期间，将基板保持在低于100℃的温度下，将铝 - 铜（Al-Cu）合金膜沉积在基板上，由此减少CuAl 2的析出。 通过在处理过程中将冷却剂气体泵送通过冷却的压板并抵靠衬底来冷却衬底。 在蚀刻之前的后续成膜也在低于100℃下进行，以防止CuAl2沉淀，直到蚀刻Al-Cu合金膜。 在蚀刻之后通过退火衬底形成大的晶粒。

公开(公告)号：US07889539B2

公开(公告)日：2011-02-15

申请号：US12653486

申请日：2009-12-14

Applicant: Darrell Rinerson ,  Wayne Kinney ,  Edmond Ward ,  Steve Kuo-Ren Hsia ,  Steven W. Longcor ,  Christophe Chevallier ,  John E. Sanchez, Jr. ,  Philip Swab

Inventor： Darrell Rinerson ,  Wayne Kinney ,  Edmond Ward ,  Steve Kuo-Ren Hsia ,  Steven W. Longcor ,  Christophe Chevallier ,  John E. Sanchez, Jr. ,  Philip Swab

IPC: G11C11/00 ,  H01L49/00

CPC classification number: H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.

公开(公告)号：US06989604B1

公开(公告)日：2006-01-24

申请号：US10672103

申请日：2003-09-26

Applicant: Christy Mei-Chu Woo ,  Minh Van Ngo ,  John E. Sanchez, Jr. ,  Steven C. Avanzino

Inventor： Christy Mei-Chu Woo ,  Minh Van Ngo ,  John E. Sanchez, Jr. ,  Steven C. Avanzino

IPC: H01L23/52

CPC classification number: H01L21/76843 ,  H01L21/32051 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76871 ,  H01L21/76876 ,  H01L2221/1089

Abstract: An integrated circuit having a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.

Abstract translation: 一种在其上具有基板和半导体器件的集成电路。 衬底上的停止层具有形成在其上的第一电介质层，其上形成有第一共形势垒的开口。 在开口中形成第一共形阻挡衬里，加工和处理以改善粘附性。 侧壁上的第一共形阻挡衬里的部分作为导体芯材料扩散到第一介电层的障碍。 导体材料形成在第一共形阻挡衬里和第一止挡层的垂直部分上的开口中。

公开(公告)号：US06723635B1

公开(公告)日：2004-04-20

申请号：US10115245

申请日：2002-04-04

Applicant: Minh Van Ngo ,  Christy Mei-Chu Woo ,  Steven C. Avanzino ,  John E. Sanchez, Jr. ,  Suzette K. Pangrle

Inventor： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Steven C. Avanzino ,  John E. Sanchez, Jr. ,  Suzette K. Pangrle

IPC: H01L214763

CPC classification number: H01L21/76831 ,  H01L21/76807

Abstract: Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.

Abstract translation: 通过在阻挡金属层沉积之前沉积具有富硅表面的薄的，保形的碳化硅衬垫，可以防止在大马士革加工过程中低k ILD降解。 实施例包括在多孔低k电介质层中形成双镶嵌开口，沉积具有衬在开口上的富硅表面的薄碳化硅衬垫，沉积阻挡金属层，例如Ta / TaN复合材料，并用 铜。

公开(公告)号：US07701834B2

公开(公告)日：2010-04-20

申请号：US11037971

申请日：2005-01-18

Applicant: Darrell Rinerson ,  Christophe Chevallier ,  John E. Sanchez, Jr. ,  Lawerence Schloss

Inventor： Darrell Rinerson ,  Christophe Chevallier ,  John E. Sanchez, Jr. ,  Lawerence Schloss

IPC: G11B9/00

CPC classification number: G11B9/08 ,  B82Y10/00 ,  G11B9/1445

Abstract: A movable terminal in a two terminal memory array. A storage medium is disposed between two terminals, one of the terminals being movable relative to the second terminal. Either one of the terminals or both terminals might actually move, resulting in one terminal being moved relative to the other terminal. A memory element disposed between the two terminals has a conductance that is responsive to a write voltage across the electrodes.

Abstract translation: 二端存储器阵列中的可动端子。 存储介质设置在两个端子之间，其中一个端子可相对于第二端子移动。 终端或两个终端中的任一个可能实际上移动，导致一个终端相对于另一个终端移动。 设置在两个端子之间的存储元件具有响应电极两端的写入电压的电导。

公开(公告)号：US07394679B2

公开(公告)日：2008-07-01

申请号：US11473005

申请日：2006-06-22

Applicant: Darrell Rinerson ,  Wayne Kinney ,  Edmond Ward ,  Steve Kuo-Ren Hsia ,  Steven W. Longcor ,  Christophe Chevallier ,  John E. Sanchez, Jr. ,  Philip Swab

Inventor： Darrell Rinerson ,  Wayne Kinney ,  Edmond Ward ,  Steve Kuo-Ren Hsia ,  Steven W. Longcor ,  Christophe Chevallier ,  John E. Sanchez, Jr. ,  Philip Swab

IPC: G11C11/00

CPC classification number: H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.

Abstract translation: 提供经处理的导电元件。 可以通过在导电元件上沉积反应性金属或非常薄的材料层来处理导电元件。 反应性金属（或非常薄的材料层）通常将夹在导电元件和电极之间。 该结构还具有非线性IV特性，这在某些阵列中是有利的。

公开(公告)号：US06836017B2

公开(公告)日：2004-12-28

申请号：US10759170

申请日：2004-01-20

Applicant: Minh Van Ngo ,  Christy Mei-Chu Woo ,  Steven C. Avanzino ,  John E. Sanchez, Jr. ,  Suzette K. Pangrle

Inventor： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Steven C. Avanzino ,  John E. Sanchez, Jr. ,  Suzette K. Pangrle

IPC: H01L2348

CPC classification number: H01L21/76831 ,  H01L21/76807

Abstract: Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.

Abstract translation: 通过在阻挡金属层沉积之前沉积具有富硅表面的薄的，保形的碳化硅衬垫，可以防止在大马士革加工过程中低k ILD降解。 实施例包括在多孔低k电介质层中形成双镶嵌开口，沉积具有衬在开口上的富硅表面的薄碳化硅衬垫，沉积阻挡金属层，例如Ta / TaN复合材料，并用 铜。