知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

182 条记录 (耗时 0.024 秒)

    Multi-layer barrier layer for interconnect structure
    1.
    发明授权
    Multi-layer barrier layer for interconnect structure 有权
    用于互连结构的多层阻挡层

    公开(公告)号：US08728931B2

    公开(公告)日：2014-05-20

    申请号：US13553977

    申请日：2012-07-20

    申请人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

    发明人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/49866 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/49827 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.

    摘要翻译： 形成互连结构的方法包括在基板的电介质层中形成凹部。 形成粘合阻挡层以使凹部成线。 第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。 在粘合阻挡层上方形成有应力降低阻挡层。 所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。 该凹部填充有填充层。

    Method to reduce MOL damage on NiSi
    3.
    发明授权
    Method to reduce MOL damage on NiSi 有权
    减少NiSi上MOL损伤的方法

    公开(公告)号：US07994038B2

    公开(公告)日：2011-08-09

    申请号：US12366378

    申请日：2009-02-05

    申请人： Karthik Ramani ,  Paul R. Besser

    发明人： Karthik Ramani ,  Paul R. Besser

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/823807 ,  H01L21/28052 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/458 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7843

    摘要： Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface. The platinum concentration gradient protects the nickel silicide layer during subsequent processing, as during etching to remove overlying stress liners, thereby avoiding a decrease in device performance.

    摘要翻译： 晶体管器件形成有硅化镍层，配制成防止去除上覆应力衬垫时的退化。 实施方案包括具有镍化硅层的晶体管，其铂组分梯度朝向其上表面增加铂含量，即铂在远离栅电极和源/漏区的方向上增加。 实施例包括形成具有第一量的铂的第一镍层，并在第一层镍上形成具有第二量铂的第二层镍，第二重量百分比的铂大于第一重量百分数。 然后将镍层退火以形成铂化合物梯度朝向上表面逐渐增加的铂硅化镍层。 铂浓度梯度在后续处理期间保护硅化镍层，如在蚀刻期间去除上覆的应力衬垫，从而避免器件性能的降低。

    Semiconductor device and method of manufacturing a semiconductor device
    4.
    发明授权
    Semiconductor device and method of manufacturing a semiconductor device 有权
    半导体装置及其制造方法

    公开(公告)号：US07910996B2

    公开(公告)日：2011-03-22

    申请号：US12496133

    申请日：2009-07-01

    申请人： Paul R. Besser ,  Scott D. Luning

    发明人： Paul R. Besser ,  Scott D. Luning

    IPC分类号： H01L29/12

    CPC分类号： H01L29/66628 ,  H01L29/66772

    摘要： A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.

    摘要翻译： 公开了一种半导体器件，其具有覆盖具有主表面的半导体层的导电栅极结构。 隔离材料凹陷在半导体层的主表面下方的沟槽区域内。 形成外延层，覆盖主表面的一部分和形成沟槽侧壁的有源区。

    MOS TRANSISTORS HAVING NiPtSi CONTACT LAYERS AND METHODS FOR FABRICATING THE SAME
    5.
    发明申请
    MOS TRANSISTORS HAVING NiPtSi CONTACT LAYERS AND METHODS FOR FABRICATING THE SAME 审中-公开
    具有NiPtSi接触层的MOS晶体管及其制造方法

    公开(公告)号：US20090127594A1

    公开(公告)日：2009-05-21

    申请号：US11942094

    申请日：2007-11-19

    申请人： Valli ARUNACHALAM ,  Paul R. BESSER

    发明人： Valli ARUNACHALAM ,  Paul R. BESSER

    IPC分类号： H01L21/441 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L21/28518 ,  H01L21/2855

    摘要： MOS transistors and methods for fabricating MOS transistors are provided. One exemplary method comprises providing a silicon substrate having an impurity-doped region disposed at a surface of the silicon substrate. A first layer is sputter-deposited onto the impurity-doped region using a first sputtering target comprising nickel and a first concentration of platinum. A second layer is sputter-deposited onto the first layer using a second sputtering target comprising nickel and a second concentration of platinum, wherein the second concentration of platinum is less than the first.

    摘要翻译： 提供了用于制造MOS晶体管的MOS晶体管和方法。 一种示例性方法包括提供硅衬底，其具有设置在硅衬底的表面处的杂质掺杂区域。 使用包含镍和第一浓度的铂的第一溅射靶将第一层溅射沉积到杂质掺杂区域上。 使用包含镍和第二浓度铂的第二溅射靶溅射沉积到第一层上，其中第二浓度的铂小于第一层。

    Method for manufacturing a semiconductor component that inhibits formation of wormholes
    8.
    发明授权
    Method for manufacturing a semiconductor component that inhibits formation of wormholes 有权
    制造抑制虫洞形成的半导体部件的方法

    公开(公告)号：US07217660B1

    公开(公告)日：2007-05-15

    申请号：US11109964

    申请日：2005-04-19

    申请人： Connie Pin-Chin Wang ,  Paul R. Besser ,  Jinsong Yin ,  Hieu T. Pham ,  Minh Van Ngo

    发明人： Connie Pin-Chin Wang ,  Paul R. Besser ,  Jinsong Yin ,  Hieu T. Pham ,  Minh Van Ngo

    IPC分类号： H01L21/22

    CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76846 ,  H01L29/6659

    摘要： A method for manufacturing a semiconductor component that inhibits formation of wormholes in a semiconductor substrate. A contact opening is formed in a dielectric layer disposed on a semiconductor substrate. The contact opening exposes a portion of the semiconductor substrate. A sacrificial layer of oxide is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact opening. Silane is reacted with tungsten hexafluoride to form a hydrofluoric acid vapor and tungsten. The hydrofluoric acid vapor etches away the sacrificial oxide layer and a thin layer of tungsten is formed on the exposed portion of the semiconductor substrate. After forming the thin layer of tungsten, the reactants may be changed to more quickly fill the contact opening with tungsten.

    摘要翻译： 一种制造半导体元件的方法，该半导体元件抑制在半导体衬底中形成虫洞。 在设置在半导体衬底上的电介质层中形成接触开口。 接触开口露出半导体衬底的一部分。 在半导体衬底的暴露部分上并沿着接触开口的侧壁形成氧化物牺牲层。 硅烷与六氟化钨反应形成氢氟酸蒸汽和钨。 氢氟酸蒸气蚀刻掉牺牲氧化物层，并且在半导体衬底的暴露部分上形成薄的钨层。 在形成钨的薄层之后，可以改变反应物以更快地用钨填充接触开口。

    Low power pre-silicide process in integrated circuit technology
    9.
    发明授权
    Low power pre-silicide process in integrated circuit technology 有权
    集成电路技术中的低功耗预硅化工艺

    公开(公告)号：US07049666B1

    公开(公告)日：2006-05-23

    申请号：US10859286

    申请日：2004-06-01

    申请人： Robert J. Chiu ,  Jeffrey P. Patton ,  Paul R. Besser ,  Minh Van Ngo

    发明人： Robert J. Chiu ,  Jeffrey P. Patton ,  Paul R. Besser ,  Minh Van Ngo

    IPC分类号： H01L29/94 ,  H01L21/44

    CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A thin insulating layer is formed over the source/drain junctions. A silicide is formed on the thin insulating layer and on the gate. An interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.

    摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结上形成一个薄的绝缘层。 在薄绝缘层和栅极上形成硅化物。 在半导体衬底上沉积层间电介质。 然后在层间电介质中形成与硅化物的接触。