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23 条记录 (耗时 0.014 秒)

    Multi-layer barrier layer for interconnect structure
    1.
    发明授权
    Multi-layer barrier layer for interconnect structure 有权
    用于互连结构的多层阻挡层

    公开(公告)号：US09269615B2

    公开(公告)日：2016-02-23

    申请号：US13554020

    申请日：2012-07-20

    申请人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

    发明人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

    IPC分类号： H01L21/768 ,  H01L23/532

    CPC分类号： H01L21/76873 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.

    摘要翻译： 形成互连结构的方法包括在基板的电介质层中形成凹部。 形成粘合阻挡层以使凹部成线。 第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。 在粘合阻挡层上方形成有应力降低阻挡层。 所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。 该凹部填充有填充层。

    METHOD FOR REDUCING WETTABILITY OF INTERCONNECT MATERIAL AT CORNER INTERFACE AND DEVICE INCORPORATING SAME
    2.
    发明申请
    METHOD FOR REDUCING WETTABILITY OF INTERCONNECT MATERIAL AT CORNER INTERFACE AND DEVICE INCORPORATING SAME 有权
    用于降低角接触面上的互连材料的湿度的方法和包含其的装置

    公开(公告)号：US20140027910A1

    公开(公告)日：2014-01-30

    申请号：US13561195

    申请日：2012-07-30

    申请人： Xunyuan Zhang ,  Hoon Kim ,  Vivian W. Ryan

    发明人： Xunyuan Zhang ,  Hoon Kim ,  Vivian W. Ryan

    IPC分类号： H01L23/532 ,  H01L21/321

    CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate, forming a first transition metal layer in the recess on corner portions of the recess, and forming a second transition metal layer in the recess over the first transition metal layer to line the recess. The method further includes filling the recess with a fill layer and annealing the substrate so that the first transition metal layer and the second transition metal layer form an alloy portion proximate the corner portions during the annealing, the alloy portion having a reduced wettability for a material of the fill layer than the second transition metal. Additionally, the method includes polishing the substrate to remove portions of the fill layer extending above the recess.

    摘要翻译： 形成互连结构的方法包括在基板的电介质层中形成凹部，在凹部的凹部中的凹部中形成第一过渡金属层，并在第一过渡金属的凹部中形成第二过渡金属层 层到凹槽。 该方法还包括用填充层填充凹槽并退火基板，使得第一过渡金属层和第二过渡金属层在退火期间在拐角部分附近形成合金部分，合金部分对于材料的润湿性降低 的填充层比第二过渡金属。 另外，该方法包括抛光衬底以去除在凹部上方延伸的填充层的部分。

    Stress migration evaluation method
    5.
    发明授权
    Stress migration evaluation method 失效
    压力迁移评估方法

    公开(公告)号：US5930587A

    公开(公告)日：1999-07-27

    申请号：US917955

    申请日：1997-08-27

    申请人： Vivian W. Ryan

    发明人： Vivian W. Ryan

    IPC分类号： H01L21/66 ,  H01L21/44

    CPC分类号： H01L22/24 ,  Y10S148/003 ,  Y10S148/162 ,  Y10S438/927

    摘要： A method for accurately and objectively evaluating stress migration effects on long term reliability of integrated circuits. A sample containing a conductive runner is fabricated according to a given fabrication process. The fabricated sample undergoes a heating step at a first temperature for a first time period to induce material interactions at an accelerated rate, followed by cooling the sample to a second temperature and maintaining the second temperature for a time of sufficient duration such that relaxation occurs. Then the sample undergoes a heating process at a third temperature for a time sufficient to nucleate a predetermined number of voids, followed by heating the sample runner at a fourth temperature, less than than the third temperature, to propagate the voids such that a maximum void size is determined. Void distribution is preferably monitored by optical and scanning electron microscopy. By analyzing the void size distribution data for the isothermal void propagation annealing, a measure of the long term reliability is provided.

    摘要翻译： 准确，客观地评估应力迁移对集成电路长期可靠性的影响的方法。 根据给定的制造工艺制造包含导电流道的样品。 所制造的样品在第一温度下经历加热步骤，以第一时间段以加速速率诱导材料相互作用，随后将样品冷却至第二温度，并将第二温度保持足够的持续时间以使得发生弛豫。 然后，样品在第三温度下进行加热过程足以将预定数量的空隙成核，然后在小于第三温度的第四温度下加热样品流道，以使空隙传播，使得最大空隙 尺寸是确定的。 优选通过光学和扫描电子显微镜监测空隙分布。 通过分析等温空隙传播退火的孔径分布数据，提供了长期可靠性的测量。

    Conductive runner fabrication
    6.
    发明授权
    Conductive runner fabrication 失效
    导电流道制造

    公开(公告)号：US5599737A

    公开(公告)日：1997-02-04

    申请号：US367380

    申请日：1994-12-30

    申请人： Vivian W. Ryan

    发明人： Vivian W. Ryan

    IPC分类号： H01L21/3213 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L21/283

    CPC分类号： H01L21/76838 ,  Y10S438/927

    摘要： The method of forming runners having superior stress migration characteristics is disclosed. A blanket layer of conductive material is deposited over a dielectric. A blanket layer is subjected to a blanket-etch back procedure, thereby reducing its thickness by approximately half. The remaining layer is then patterned to form runners. Resulting runners have a superior grain structure and greater resistance to electromigration and stress migration.

    摘要翻译： 公开了形成具有优异的应力迁移特性的浇道的方法。 导电材料的覆盖层沉积在电介质上。 橡皮布层经受覆盖 - 回蚀程序，从而将其厚度减小大约一半。 然后将剩余的层图案化以形成流道。 所得流动剂具有优异的晶粒结构和更大的抗电迁移和应力迁移的能力。

    Strain-compensating fill patterns for controlling semiconductor chip package interactions
    8.
    发明授权
    Strain-compensating fill patterns for controlling semiconductor chip package interactions 有权
    用于控制半导体芯片封装相互作用的应变补偿填充图案

    公开(公告)号：US08441131B2

    公开(公告)日：2013-05-14

    申请号：US13230457

    申请日：2011-09-12

    申请人： Vivian W. Ryan

    发明人： Vivian W. Ryan

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763

    CPC分类号： H01L23/522 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/06164 ,  H01L2224/06179 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/3511 ,  H01L2224/14164 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

    摘要： Generally, the subject matter disclosed herein relates to sophisticated semiconductor chips that may be less susceptible to the occurrence of white bumps during semiconductor chip packaging operations, such as flip-chip or 3D-chip assembly, and the like. One illustrative semiconductor chip disclosed herein includes, among other things, a bond pad and a metallization layer below the bond pad, wherein the metallization layer is made up of a bond pad area below the bond pad and a field area surrounding the bond pad area. Additionally, the semiconductor device also includes a plurality of device features in the metallization layer, wherein the plurality of device features has a first feature density in the bond pad area and a second feature density in the field area that is less than the first feature density.

    摘要翻译： 通常，本文公开的主题涉及在半导体芯片封装操作（例如倒装芯片或3D芯片组装）期间可能不太容易发生白色凸起的复杂半导体芯片。 本文公开的一个说明性的半导体芯片尤其包括在接合焊盘下方的接合焊盘和金属化层，其中金属化层由接合焊盘下方的接合焊盘区域和围绕接合焊盘区域的场区域组成。 另外，半导体器件还包括金属化层中的多个器件特征，其中多个器件特征在接合焊盘区域中具有第一特征密度，并且场场区域中的第二特征密度小于第一特征密度 。

    Multi-layer barrier layer for interconnect structure
    10.
    发明授权
    Multi-layer barrier layer for interconnect structure 有权
    用于互连结构的多层阻挡层

    公开(公告)号：US08728931B2

    公开(公告)日：2014-05-20

    申请号：US13553977

    申请日：2012-07-20

    申请人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

    发明人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/49866 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/49827 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.

    摘要翻译： 形成互连结构的方法包括在基板的电介质层中形成凹部。 形成粘合阻挡层以使凹部成线。 第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。 在粘合阻挡层上方形成有应力降低阻挡层。 所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。 该凹部填充有填充层。