公开(公告)号：US08680681B2

公开(公告)日：2014-03-25

申请号：US13218555

申请日：2011-08-26

Applicant: Vivian W. Ryan

Inventor： Vivian W. Ryan

IPC: H01L23/52 ,  H01L23/48 ,  H01L23/485

CPC classification number: H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05578 ,  H01L2224/06051 ,  H01L2224/0614 ,  H01L2224/06177 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A semiconductor chip includes a composite bond pad that is electrically connected to at least one integrated circuit device. The composite bond pad includes a first bond pad portion having a first upper surface corresponding to a first surface area that is defined by a first substantially regular geometric shape when viewed from above that has a first area centroid that is located a first distance from a center of the semiconductor chip, and further includes a second bond pad portion positioned above the first upper surface and having a second upper surface that extends above the first upper surface, the second portion corresponding to a second surface area that is defined by at least a part of a second substantially regular geometric shape when viewed from above that has a second area centroid that is located a second distance from the center that is greater than the first distance.

Abstract translation: 半导体芯片包括电连接到至少一个集成电路器件的复合焊盘。 复合接合焊盘包括第一接合焊盘部分，其具有对应于第一表面区域的第一上表面，该第一表面区域由从上方观察时由第一基本上规则的几何形状限定，第一表面区域具有位于距离中心的第一距离的第一区域重心 并且还包括位于第一上表面上方并具有在第一上表面上方延伸的第二上表面的第二接合焊盘部分，第二部分对应于由至少一部分限定的第二表面区域 当从上方观察时具有第二基本上规则的几何形状，其具有位于距离中心的第二距离大于第一距离的第二区域重心。

公开(公告)号：US5243221A

公开(公告)日：1993-09-07

申请号：US1203

申请日：1993-01-05

Applicant: Vivian W. Ryan ,  Ronald J. Schutz

Inventor： Vivian W. Ryan ,  Ronald J. Schutz

IPC: H01L23/532

CPC classification number: H01L23/53219 ,  H01L23/532 ,  H01L2924/0002

Abstract: Stress induced grain boundary movement in aluminum lines used as connections in integrated circuits is substantially avoided by doping the aluminum with iron. Through this expedient not only is grain boundary movement avoided but electromigration problems are also decreased.

Abstract translation: 通过用铁掺杂铝，基本上避免了用作集成电路中的连接的铝线中的应力引起的晶界运动。 通过这种方式，不仅可以避免晶界运动，而且电迁移问题也会减少。

公开(公告)号：US4826709A

公开(公告)日：1989-05-02

申请号：US161876

申请日：1988-02-29

Applicant: Vivian W. Ryan ,  Gerald Smolinsky

Inventor： Vivian W. Ryan ,  Gerald Smolinsky

IPC: C03C3/06 ,  H01L21/316 ,  B05D3/12

CPC classification number: C03C3/06 ,  H01L21/316 ,  C03C2201/02 ,  C03C2201/10 ,  C03C2201/28 ,  C03C2203/20

Abstract: A sol-gel process is utilized for producing silicon oxide glasses useful in the manufacture of devices such as semiconductor devices. These glasses are easily deposited by techniques such as spinning. Not only is the glass easily applied, but also has advantageous electrical, etching, and mechanical properties. Thus, these glasses are useful in applications such as passivating layers for integrated circuit devices and as intermediary layers in trilevel lithography for the production of such devices.

Abstract translation: 溶胶 - 凝胶法用于生产用于制造诸如半导体器件的器件的氧化硅玻璃。 这些玻璃容易通过旋转技术沉积。 不仅玻璃容易应用，而且具有有利的电，蚀刻和机械性能。 因此，这些玻璃在诸如用于集成电路器件的钝化层和用于制造这种器件的三层光刻中的中间层的应用中是有用的。

公开(公告)号：US08623754B1

公开(公告)日：2014-01-07

申请号：US13560280

申请日：2012-07-27

Applicant: Vivian W. Ryan ,  Holm Geisler ,  Dirk Breuer

Inventor： Vivian W. Ryan ,  Holm Geisler ,  Dirk Breuer

IPC: H01L21/44

CPC classification number: H01L24/14 ,  H01L22/12 ,  H01L22/20 ,  H01L23/488 ,  H01L24/11 ,  H01L24/13 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11009 ,  H01L2224/1184 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/14051 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/742 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/3511 ,  H01L2924/3512 ,  Y10T29/53204 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Generally, the subject matter disclosed herein relates to repairing anomalous stiff pillar bumps that may be detected above a metallization system of a semiconductor chip or wafer. One illustrative method disclosed herein includes, among other things, forming a pillar bump above a metallization system of a semiconductor chip, and forming a plurality of notches in the pillar bump, wherein the plurality of notches are adapted to adjust a flexibility of the pillar bump when the pillar bump is exposed to a lateral force.

Abstract translation: 通常，本文公开的主题涉及修复可以在半导体芯片或晶片的金属化系统上方检测到的异常刚性柱状突起。 本文公开的一种说明性方法包括在半导体芯片的金属化系统之上形成柱状凸起，并且在柱状凸块中形成多个凹口，其中多个凹口适于调节柱凸起的柔性 当柱凸起暴露于横向力时。

公开(公告)号：US08441131B2

公开(公告)日：2013-05-14

申请号：US13230457

申请日：2011-09-12

Applicant: Vivian W. Ryan

Inventor： Vivian W. Ryan

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763

CPC classification number: H01L23/522 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/06164 ,  H01L2224/06179 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/3511 ,  H01L2224/14164 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Generally, the subject matter disclosed herein relates to sophisticated semiconductor chips that may be less susceptible to the occurrence of white bumps during semiconductor chip packaging operations, such as flip-chip or 3D-chip assembly, and the like. One illustrative semiconductor chip disclosed herein includes, among other things, a bond pad and a metallization layer below the bond pad, wherein the metallization layer is made up of a bond pad area below the bond pad and a field area surrounding the bond pad area. Additionally, the semiconductor device also includes a plurality of device features in the metallization layer, wherein the plurality of device features has a first feature density in the bond pad area and a second feature density in the field area that is less than the first feature density.

Abstract translation: 通常，本文公开的主题涉及在半导体芯片封装操作（例如倒装芯片或3D芯片组装）期间可能不太容易发生白色凸起的复杂半导体芯片。 本文公开的一个说明性的半导体芯片尤其包括在接合焊盘下方的接合焊盘和金属化层，其中金属化层由接合焊盘下方的接合焊盘区域和围绕接合焊盘区域的场区域组成。 另外，半导体器件还包括金属化层中的多个器件特征，其中多个器件特征在接合焊盘区域中具有第一特征密度，并且场场区域中的第二特征密度小于第一特征密度 。

公开(公告)号：US09269615B2

公开(公告)日：2016-02-23

申请号：US13554020

申请日：2012-07-20

Applicant: Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

Inventor： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76873 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.

Abstract translation: 形成互连结构的方法包括在基板的电介质层中形成凹部。 形成粘合阻挡层以使凹部成线。 第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。 在粘合阻挡层上方形成有应力降低阻挡层。 所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。 该凹部填充有填充层。

公开(公告)号：US20140027910A1

公开(公告)日：2014-01-30

申请号：US13561195

申请日：2012-07-30

Applicant: Xunyuan Zhang ,  Hoon Kim ,  Vivian W. Ryan

Inventor： Xunyuan Zhang ,  Hoon Kim ,  Vivian W. Ryan

IPC: H01L23/532 ,  H01L21/321

CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate, forming a first transition metal layer in the recess on corner portions of the recess, and forming a second transition metal layer in the recess over the first transition metal layer to line the recess. The method further includes filling the recess with a fill layer and annealing the substrate so that the first transition metal layer and the second transition metal layer form an alloy portion proximate the corner portions during the annealing, the alloy portion having a reduced wettability for a material of the fill layer than the second transition metal. Additionally, the method includes polishing the substrate to remove portions of the fill layer extending above the recess.

Abstract translation: 形成互连结构的方法包括在基板的电介质层中形成凹部，在凹部的凹部中的凹部中形成第一过渡金属层，并在第一过渡金属的凹部中形成第二过渡金属层 层到凹槽。 该方法还包括用填充层填充凹槽并退火基板，使得第一过渡金属层和第二过渡金属层在退火期间在拐角部分附近形成合金部分，合金部分对于材料的润湿性降低 的填充层比第二过渡金属。 另外，该方法包括抛光衬底以去除在凹部上方延伸的填充层的部分。

公开(公告)号：US20140021613A1

公开(公告)日：2014-01-23

申请号：US13553977

申请日：2012-07-20

Applicant: Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

Inventor： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/49866 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/49827 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.

公开(公告)号：US06410435B1

公开(公告)日：2002-06-25

申请号：US09410686

申请日：1999-10-01

Applicant: Vivian W. Ryan

Inventor： Vivian W. Ryan

IPC: H01L2144

CPC classification number: H01L21/76849 ,  H01L21/76843 ,  H01L23/53238 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/85375 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for manufacturing integrated circuits; particularly, a method for fabricating a copper interconnect system and a copper interconnect system, having a layer of CrO, fabricated by the method.

Abstract translation: 一种制造集成电路的方法; 特别是通过该方法制造的具有CrO层的铜互连系统和铜互连系统的制造方法。

公开(公告)号：US5930587A

公开(公告)日：1999-07-27

申请号：US917955

申请日：1997-08-27

Applicant: Vivian W. Ryan

Inventor： Vivian W. Ryan

IPC: H01L21/66 ,  H01L21/44

CPC classification number: H01L22/24 ,  Y10S148/003 ,  Y10S148/162 ,  Y10S438/927

Abstract: A method for accurately and objectively evaluating stress migration effects on long term reliability of integrated circuits. A sample containing a conductive runner is fabricated according to a given fabrication process. The fabricated sample undergoes a heating step at a first temperature for a first time period to induce material interactions at an accelerated rate, followed by cooling the sample to a second temperature and maintaining the second temperature for a time of sufficient duration such that relaxation occurs. Then the sample undergoes a heating process at a third temperature for a time sufficient to nucleate a predetermined number of voids, followed by heating the sample runner at a fourth temperature, less than than the third temperature, to propagate the voids such that a maximum void size is determined. Void distribution is preferably monitored by optical and scanning electron microscopy. By analyzing the void size distribution data for the isothermal void propagation annealing, a measure of the long term reliability is provided.

Abstract translation: 准确，客观地评估应力迁移对集成电路长期可靠性的影响的方法。 根据给定的制造工艺制造包含导电流道的样品。 所制造的样品在第一温度下经历加热步骤，以第一时间段以加速速率诱导材料相互作用，随后将样品冷却至第二温度，并将第二温度保持足够的持续时间以使得发生弛豫。 然后，样品在第三温度下进行加热过程足以将预定数量的空隙成核，然后在小于第三温度的第四温度下加热样品流道，以使空隙传播，使得最大空隙 尺寸是确定的。 优选通过光学和扫描电子显微镜监测空隙分布。 通过分析等温空隙传播退火的孔径分布数据，提供了长期可靠性的测量。