公开(公告)号：US5656830A

公开(公告)日：1997-08-12

申请号：US988849

申请日：1992-12-10

Applicant: John Harold Zechman

Inventor： John Harold Zechman

IPC: H01L21/60 ,  H01L23/29 ,  H01L23/31 ,  H01L23/49 ,  H01L23/495 ,  H01L23/552 ,  H01L23/64 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/85 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/552 ,  H01L23/642 ,  H01L24/48 ,  H01L2223/6622 ,  H01L2224/05601 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4557 ,  H01L2224/456 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/85815 ,  H01L2224/85909 ,  H01L2224/8592 ,  H01L24/45 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/30107 ,  Y10T29/49171

Abstract: A composite containing an integrated circuit chip having conductive site thereon and electrically conductive leads that are interconnected to the conductive site by electrically conductive wire; wherein the wire is coated with a dielectric material. Also, a method for fabricating the composite is provided.

Abstract translation: 包含其上具有导电位置的集成电路芯片和通过导电线互连到导电部位的导电引线的复合材料; 其中所述线被电介质材料涂覆。 另外，提供了一种制造该复合材料的方法。

公开(公告)号：US5056217A

公开(公告)日：1991-10-15

申请号：US510035

申请日：1990-04-16

Applicant: Nobuto Yamazaki ,  Akihiro Nishimura

Inventor： Nobuto Yamazaki ,  Akihiro Nishimura

IPC: H01L21/60 ,  H01L21/00 ,  H01L21/603

CPC classification number: H01L24/85 ,  H01L24/78 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/4554 ,  H01L2224/456 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/48475 ,  H01L2224/49175 ,  H01L2224/78313 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85201 ,  H01L24/45 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/30107

Abstract: Method of manufacturing semiconductor elements equipped with leads which are connected to electrodes and formed of wires including the steps of positioning each semiconductor element on a bonding stage, feeding a tip end of the wire under a bonding tool so that the bonding tool presses the tip end against the electrode to bond it to the electrode, shifting the bonding tool to away from the tip end and pressing the wire against wire-cutting section of the bonding stage, and pulling the wire away from the bonding tool to cut the wire.

Abstract translation: 制造半导体元件的制造方法，该半导体元件配备有与电极连接并由电线形成的引线，包括以下步骤：将每个半导体元件放置在接合台上，将焊丝的末端馈送在接合工具下方，使得接合工具压紧尖端 抵靠电极将其粘合到电极上，将接合工具移动到远离尖端并且将线压在接合台的线切割部分上，并且将线从接合工具拉出以切割线。

公开(公告)号：US4907734A

公开(公告)日：1990-03-13

申请号：US263806

申请日：1988-10-28

Applicant: H. Ward Conru ,  Stephen E. Gons ,  Gordon C. Osborne, Jr. ,  Douglas W. Phelps, Jr. ,  Stephen G. Starr ,  William C. Ward

Inventor： H. Ward Conru ,  Stephen E. Gons ,  Gordon C. Osborne, Jr. ,  Douglas W. Phelps, Jr. ,  Stephen G. Starr ,  William C. Ward

IPC: H01R43/00 ,  B23K20/02 ,  B23K20/10 ,  B23K20/22 ,  B23K35/00 ,  H01L21/00 ,  H01L21/607 ,  H01R43/02 ,  H05K3/32 ,  H05K3/34

CPC classification number: H01L24/85 ,  B23K20/023 ,  B23K20/10 ,  B23K20/22 ,  B23K35/007 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01R43/02 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48799 ,  H01L2224/78301 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85365 ,  H01L2224/85815 ,  H01L24/45 ,  H01L24/78 ,  H01L2924/00011 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H05K3/328 ,  H05K3/3457

Abstract: A compression bond is formed between a gold or gold alloy wire and lead/tin solder by forming a head on the wire and forcing the head into a pad of the solder by thermosonic, or thermocompression, or ultrasonic compression bonding techniques. This forms a gold/tin intermetallic compound which in turn forms the bond. The head of the wire is maintained out of contact with any underlying surface, and surrounded by the solder.

公开(公告)号：US4580713A

公开(公告)日：1986-04-08

申请号：US535055

申请日：1983-09-23

Applicant: Masao Sekibata ,  Kanji Otsuka ,  Yoshiyuki Ohzawa

Inventor： Masao Sekibata ,  Kanji Otsuka ,  Yoshiyuki Ohzawa

IPC: H05K3/32 ,  H01L21/60 ,  H01L21/607 ,  H01R4/62 ,  H01R43/02 ,  B23K20/10

CPC classification number: H01R43/0207 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/45644 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/4823 ,  H01L2224/48455 ,  H01L2224/48472 ,  H01L2224/48686 ,  H01L2224/48699 ,  H01L2224/4911 ,  H01L2224/4917 ,  H01L2224/78313 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L24/45 ,  H01L2924/00011 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/19107 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01R4/625

Abstract: A method for bonding an aluminum wire to a minute pad of an electronic circuit by an ultrasonic bonding technique. An anodized aluminum wire having its surface subjected to insulating coating is used. The bonding is effected such that this anodized aluminum wire is pressed against the pad by means of a wedge and, while a load is being thereby applied to the wire, ultrasonic vibrations are caused in the wedge. The alumite is exfoliated from the base material by application of the load and ultrasonic energy to the wire, and this base material and pad are bonded together at this exfoliated portion.

Abstract translation: 一种通过超声波接合技术将铝线结合到电子电路的微小焊盘的方法。 使用其表面经过绝缘涂层的阳极氧化铝线。 实现接合，使得该阳极氧化铝线通过楔形物压靠在焊盘上，并且当负载由此施加到电线时，在楔形件中引起超声波振动。 通过将负载和超声波能量施加到导线上，将耐酸铝从基材剥离，并且该基材和垫在该剥离部分处结合在一起。

公开(公告)号：US09362249B2

公开(公告)日：2016-06-07

申请号：US14619736

申请日：2015-02-11

Applicant: TANAKA DENSHI KOGYO K.K.

Inventor： Kazuhiko Yasuhara ,  Nanako Maeda ,  Junichi Okazaki ,  Jun Chiba ,  Wei Chen ,  Yuki Antoku

IPC: H01L23/00

CPC classification number: H01L24/45 ,  H01L24/43 ,  H01L24/48 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/05624 ,  H01L2224/43 ,  H01L2224/43848 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/456 ,  H01L2224/48247 ,  H01L2224/78601 ,  H01L2224/85045 ,  H01L2224/85203 ,  H01L2224/85207 ,  H01L2224/85439 ,  H01L2924/00011 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/013 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/01079 ,  H01L2924/01204 ,  H01L2924/01008 ,  H01L2924/00015 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/20753 ,  H01L2924/00014 ,  H01L2924/20105 ,  H01L2924/00 ,  H01L2924/01049 ,  H01L2924/01004

Abstract: The silver-gold alloy bonding wire of the present invention includes an alloy composed of not lower than 10% and not higher than 30% of gold (Au) and not lower than 30 ppm and not higher than 90 ppm of calcium (Ca) with the remainder of silver (Ag) at purity relative to a metallic element except for elements Au and Ca of 99.99% or higher, in mass percentage; a layer enriched with oxygen (O) and calcium (Ca) formed as a surface layer on the surface of the alloy; and a gold-enriched layer formed immediately below the surface layer.

Abstract translation: 本发明的银 - 金合金接合线包括由金（Au）的10％以上且30％以下且不低于30ppm且不高于90ppm的钙（Ca）组成的合金， 相对于除元素Au和Ca之外的金属元素的银（Ag）的剩余部分为99.99％以上，以质量％计; 在合金表面上形成有作为表面层的氧（O）和钙（Ca）的富集层; 以及形成在表面层正下方的金富集层。

公开(公告)号：US20160093586A1

公开(公告)日：2016-03-31

申请号：US14619736

申请日：2015-02-11

Applicant: TANAKA DENSHI KOGYO K.K.

Inventor： Kazuhiko YASUHARA ,  Nanako MAEDA ,  Junichi OKAZAKI ,  Jun CHIBA ,  Wei CHEN ,  Yuki ANTOKU

IPC: H01L23/00

CPC classification number: H01L24/45 ,  H01L24/43 ,  H01L24/48 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/05624 ,  H01L2224/43 ,  H01L2224/43848 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/456 ,  H01L2224/48247 ,  H01L2224/78601 ,  H01L2224/85045 ,  H01L2224/85203 ,  H01L2224/85207 ,  H01L2224/85439 ,  H01L2924/00011 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/013 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/01079 ,  H01L2924/01204 ,  H01L2924/01008 ,  H01L2924/00015 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/20753 ,  H01L2924/00014 ,  H01L2924/20105 ,  H01L2924/00 ,  H01L2924/01049 ,  H01L2924/01004

Abstract: The silver-gold alloy bonding wire of the present invention includes an alloy composed of not lower than 10% and not higher than 30% of gold (Au) and not lower than 30 ppm and not higher than 90 ppm of calcium (Ca) with the remainder of silver (Ag) at purity relative to a metallic element except for elements Au and Ca of 99.99% or higher, in mass percentage; a layer enriched with oxygen (O) and calcium (Ca) formed as a surface layer on the surface of the alloy; and a gold-enriched layer formed immediately below the surface layer.

Abstract translation: 本发明的银 - 金合金接合线包括由金（Au）的10％以上且30％以下且不低于30ppm且不高于90ppm的钙（Ca）组成的合金， 相对于除元素Au和Ca之外的金属元素的银（Ag）的剩余部分为99.99％以上，以质量％计; 在合金表面上形成有作为表面层的氧（O）和钙（Ca）的富集层; 以及形成在表面层正下方的金富集层。

公开(公告)号：US09171819B2

公开(公告)日：2015-10-27

申请号：US14511158

申请日：2014-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol-woo Lee ,  Ji-han Ko

IPC: H01L23/52 ,  H01L23/00

CPC classification number: H01L24/32 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49575 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/06135 ,  H01L2224/27003 ,  H01L2224/27436 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/3201 ,  H01L2224/32013 ,  H01L2224/32014 ,  H01L2224/32053 ,  H01L2224/32056 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/32105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/4886 ,  H01L2224/48866 ,  H01L2224/48881 ,  H01L2224/48884 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/83856 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/8546 ,  H01L2224/92147 ,  H01L2224/92165 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/06 ,  H01L2924/10161 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/13091 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/14511 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/35 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/066 ,  H01L2924/05442 ,  H01L2224/83

Abstract: Provided is a semiconductor package that may prevent deformation of stacked semiconductor chips and minimize a semiconductor package size. The semiconductor package includes a package base substrate, a lower chip stacked on the package base substrate, an upper chip stacked on the lower chip, and a first die attach film (DAF) attached to a bottom surface of the upper chip to cover at least a portion of the lower chip. The first DAF may be a multi-layer film including a first attaching layer contacting the bottom surface of the upper chip and a second attaching layer attached to a bottom of the first attaching layer to cover at least a portion of a side surface of the lower chip.

Abstract translation: 提供了可以防止堆叠的半导体芯片的变形并使半导体封装尺寸最小化的半导体封装。 半导体封装包括封装基底基板，堆叠在封装基底基板上的下部芯片，堆叠在下部芯片上的上部芯片，以及附接到上部芯片的底表面上的至少覆盖的第一芯片附着膜（DAF） 下部芯片的一部分。 第一DAF可以是多层膜，其包括接触上芯片的底表面的第一附着层和附接到第一附着层的底部的第二附着层，以覆盖下层的侧表面的至少一部分 芯片。

公开(公告)号：US20150294924A1

公开(公告)日：2015-10-15

申请号：US14552497

申请日：2014-11-25

Applicant: Zhigang Bai ,  Jinzhong Yao ,  Lan Chu Tan

Inventor： Zhigang Bai ,  Jinzhong Yao ,  Lan Chu Tan

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/58 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/85 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a first lead frame type having a first type of package leads and a pre-molded portion, and a second lead frame type having a second type of package leads that surround a die pad and are supported by the pre-molded portion. An integrated circuit is attached to the die pad and electrically connected to the first and second types of leads with bond wires. A mold compound, which forms a mold cap, covers the first and second lead frame types, the integrated circuit and the bond wires. The first lead frame type may be a QFP type and the second lead frame type may be a QFN type.

Abstract translation: 半导体封装包括具有第一类型的封装引线和预成型部分的第一引线框架型和具有围绕芯片焊盘并由预模制部分支撑的第二类型的封装引线的第二引线框架型 。 集成电路附接到管芯焊盘并且用接合线电连接到第一和第二类型的引线。 形成模具帽的模具复合体覆盖第一和第二引线框架类型，集成电路和接合线。 第一引线框类型可以是QFP型，第二引线框类型可以是QFN型。

公开(公告)号：US08664752B2

公开(公告)日：2014-03-04

申请号：US13430347

申请日：2012-03-26

Applicant: Oseob Jeon ,  Yoonhwa Choi ,  Boon Huan Gooi ,  Maria Cristina B. Estacio ,  David Chong ,  Tan Teik Keng ,  Shibaek Nam ,  Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer ,  Lay Yeap Lim ,  Byoung-Ok Lee

Inventor： Oseob Jeon ,  Yoonhwa Choi ,  Boon Huan Gooi ,  Maria Cristina B. Estacio ,  David Chong ,  Tan Teik Keng ,  Shibaek Nam ,  Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer ,  Lay Yeap Lim ,  Byoung-Ok Lee

IPC: H01L23/495

CPC classification number: H01L24/29 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/16 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/45644 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/4943 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85013 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/37099

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract translation: 公开了半导体管芯封装。 示例性半导体管芯封装包括预成型衬底。 预成型基板可以具有附接到其上的半导体管芯，并且封装材料可以设置在半导体管芯上方。

公开(公告)号：US08525192B2

公开(公告)日：2013-09-03

申请号：US13246682

申请日：2011-09-27

Applicant: Yong Liu ,  Zhongfa Yuan

Inventor： Yong Liu ,  Zhongfa Yuan

IPC: H01L27/15 ,  H01L31/12 ,  H01L33/00

CPC classification number: H01L23/49861 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L25/167 ,  H01L33/483 ,  H01L33/60 ,  H01L2224/05553 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/01108 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A package is disclosed. The package includes a premolded substrate having a leadframe structure, a first device attached to the leadframe structure, and a molding material covering at least part of the leadframe structure and the first device. It also includes a second device attached to the premolded substrate.

Abstract translation: 公开了一个包装。 该封装包括具有引线框结构的预成型基板，附接到引线框架结构的第一器件和覆盖引线框结构和第一器件的至少一部分的成型材料。 它还包括连接到预成型基板的第二装置。