METHOD OF MAKING AND DESIGNING LEAD FRAMES FOR SEMICONDUCTOR PACKAGES
    5.
    发明申请
    METHOD OF MAKING AND DESIGNING LEAD FRAMES FOR SEMICONDUCTOR PACKAGES 有权
    制造和设计半导体封装的引线框架的方法

    公开(公告)号:US20090236711A1

    公开(公告)日:2009-09-24

    申请号:US12052871

    申请日:2008-03-21

    Abstract: A lead frame with patterned conductive runs on the top surface to accept a wire bonded or flip-chip or COL configuration is disclosed. The top pattern is completed and the bottom is etched away creating cavities. The cavities are filled with a pre-mold material that lend structural support of the lead frame. The top is then etch through the lead frame to the pre-mold, except with the top conductive runs exist. In this manner the conductive runs are completed and isolated from each other so that the placement of the runs is flexible. The chips are mounted and the encapsulated and the lead frames are singulated. The pattern on the top and the bottom may be defined by first plated the patterns desired.

    Abstract translation: 公开了一种在顶表面上具有带图案导电的导线框架,以接受导线接合或倒装芯片或COL构造。 顶部图案完成,底部被蚀刻掉,形成空腔。 这些空腔填充有借助引线框架的结构支撑的预模具材料。 然后将顶部通过引线框架蚀刻到预模具,除了存在顶部导电性运行。 以这种方式,导电运行完成并彼此隔离,使得运行的放置是柔性的。 芯片被安装,封装和引线框架被分割。 顶部和底部的图案可以通过首先电镀所需的图案来定义。

    Method of making and designing lead frames for semiconductor packages
    10.
    发明授权
    Method of making and designing lead frames for semiconductor packages 有权
    制造和设计半导体封装引线框架的方法

    公开(公告)号:US08110447B2

    公开(公告)日:2012-02-07

    申请号:US12052871

    申请日:2008-03-21

    Abstract: A lead frame with patterned conductive runs on the top surface to accept a wire bonded or flip-chip or COL configuration is disclosed. The top pattern is completed and the bottom is etched away creating cavities. The cavities are filled with a pre-mold material that lend structural support of the lead frame. The top is then etch through the lead frame to the pre-mold, except with the top conductive runs exist. In this manner the conductive runs are completed and isolated from each other so that the placement of the runs is flexible. The chips are mounted and the encapsulated and the lead frames are singulated. The pattern on the top and the bottom may be defined by first plated the patterns desired.

    Abstract translation: 公开了一种在顶表面上具有带图案导电的导线框架,以接受导线接合或倒装芯片或COL构造。 顶部图案完成,底部被蚀刻掉,形成空腔。 这些空腔填充有借助引线框架的结构支撑的预模具材料。 然后将顶部通过引线框架蚀刻到预模具,除了存在顶部导电性运行。 以这种方式,导电运行完成并彼此隔离,使得运行的放置是柔性的。 芯片被安装,封装和引线框架被分割。 顶部和底部的图案可以通过首先电镀所需的图案来定义。

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