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1.发明申请公开(公告)号：US20200075545A1
公开(公告)日：2020-03-05
申请号：US16382376
申请日：2019-04-12
发明人： Won-keun KIM , Kyung-suk Oh , Ji-han Ko , Kil-soo Kim , Yeong-seok Kim , Joung-phil Lee , Hwa-il Jin , Su-jung Hyung
IPC分类号： H01L25/065 , H01L23/31 , H01L23/552 , H01L23/367 , H01L25/00 , H01L21/56
摘要： A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.
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公开(公告)号：US11205637B2
公开(公告)日：2021-12-21
申请号：US17009886
申请日：2020-09-02
发明人： Won-keun Kim , Kyung-suk Oh , Ji-han Ko , Kil-soo Kim , Yeong-seok Kim , Joung-phil Lee , Hwa-il Jin , Su-jung Hyung
IPC分类号： H01L25/065 , H01L21/56 , H01L23/31 , H01L23/367 , H01L23/552 , H01L25/00
摘要： A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.
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公开(公告)号：US10797021B2
公开(公告)日：2020-10-06
申请号：US16382376
申请日：2019-04-12
发明人： Won-keun Kim , Kyung-suk Oh , Ji-han Ko , Kil-soo Kim , Yeong-seok Kim , Joung-phil Lee , Hwa-il Jin , Su-jung Hyung
IPC分类号： H01L25/065 , H01L21/56 , H01L23/31 , H01L23/367 , H01L23/552 , H01L25/00
摘要： A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.
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公开(公告)号：US09171819B2
公开(公告)日：2015-10-27
申请号：US14511158
申请日：2014-10-09
发明人： Cheol-woo Lee , Ji-han Ko
CPC分类号： H01L24/32 , H01L23/3128 , H01L23/3135 , H01L23/49575 , H01L23/49816 , H01L23/49838 , H01L24/05 , H01L24/06 , H01L24/27 , H01L24/29 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/04042 , H01L2224/05554 , H01L2224/0558 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2224/06135 , H01L2224/27003 , H01L2224/27436 , H01L2224/29082 , H01L2224/29084 , H01L2224/2919 , H01L2224/2929 , H01L2224/29387 , H01L2224/3201 , H01L2224/32013 , H01L2224/32014 , H01L2224/32053 , H01L2224/32056 , H01L2224/32058 , H01L2224/32059 , H01L2224/32105 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45169 , H01L2224/45184 , H01L2224/45565 , H01L2224/456 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/48247 , H01L2224/48824 , H01L2224/48844 , H01L2224/48847 , H01L2224/48855 , H01L2224/4886 , H01L2224/48866 , H01L2224/48881 , H01L2224/48884 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2224/83191 , H01L2224/83192 , H01L2224/83201 , H01L2224/83856 , H01L2224/85444 , H01L2224/85455 , H01L2224/8546 , H01L2224/92147 , H01L2224/92165 , H01L2224/92242 , H01L2224/92247 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2924/06 , H01L2924/10161 , H01L2924/10252 , H01L2924/10253 , H01L2924/10272 , H01L2924/10329 , H01L2924/10333 , H01L2924/10335 , H01L2924/13091 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/14511 , H01L2924/15311 , H01L2924/181 , H01L2924/35 , H01L2924/3511 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/0635 , H01L2924/0665 , H01L2924/066 , H01L2924/05442 , H01L2224/83
摘要： Provided is a semiconductor package that may prevent deformation of stacked semiconductor chips and minimize a semiconductor package size. The semiconductor package includes a package base substrate, a lower chip stacked on the package base substrate, an upper chip stacked on the lower chip, and a first die attach film (DAF) attached to a bottom surface of the upper chip to cover at least a portion of the lower chip. The first DAF may be a multi-layer film including a first attaching layer contacting the bottom surface of the upper chip and a second attaching layer attached to a bottom of the first attaching layer to cover at least a portion of a side surface of the lower chip.
摘要翻译： 提供了可以防止堆叠的半导体芯片的变形并使半导体封装尺寸最小化的半导体封装。 半导体封装包括封装基底基板，堆叠在封装基底基板上的下部芯片，堆叠在下部芯片上的上部芯片，以及附接到上部芯片的底表面上的至少覆盖的第一芯片附着膜（DAF） 下部芯片的一部分。 第一DAF可以是多层膜，其包括接触上芯片的底表面的第一附着层和附接到第一附着层的底部的第二附着层，以覆盖下层的侧表面的至少一部分 芯片。
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