公开(公告)号：US11205637B2

公开(公告)日：2021-12-21

申请号：US17009886

申请日：2020-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-keun Kim ,  Kyung-suk Oh ,  Ji-han Ko ,  Kil-soo Kim ,  Yeong-seok Kim ,  Joung-phil Lee ,  Hwa-il Jin ,  Su-jung Hyung

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/552 ,  H01L25/00

Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.

公开(公告)号：US10043780B2

公开(公告)日：2018-08-07

申请号：US15435286

申请日：2017-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-won Choi ,  Won-keun Kim ,  Myung-sung Kang ,  Gwang-sun Seo

IPC: H01L29/40 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip including a first through-silicon via (TSV), a second semiconductor chip stacked on the first semiconductor chip and including a second TSV, and a non-conductive film formed between the first semiconductor chip and the second semiconductor chip. The non-conductive film includes two layers having different viscosities.

公开(公告)号：US08901727B2

公开(公告)日：2014-12-02

申请号：US13774209

申请日：2013-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myun-sung Kang ,  Jung-min Ko ,  Sang-sick Park ,  Won-keun Kim ,  Ji-seok Hong

IPC: H01L25/10 ,  H01L23/28 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/28 ,  H01L21/486 ,  H01L21/563 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1017 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor package comprises a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a third semiconductor chip on the second semiconductor chip and a fourth semiconductor chip on the third semiconductor chip. A first underfill layer is positioned between the second semiconductor chip and the first semiconductor chip; a second underfill layer is positioned between the third semiconductor chip and the second semiconductor chip, and a third underfill layer is positioned between the fourth semiconductor chip and the third semiconductor chip. In some embodiments, the second underfill layer comprises a material that is different than the first and third underfill layers.

Abstract translation: 半导体封装包括第一半导体芯片，第一半导体芯片上的第二半导体芯片，第二半导体芯片上的第三半导体芯片和第三半导体芯片上的第四半导体芯片。 第一底部填充层位于第二半导体芯片和第一半导体芯片之间; 第二底部填充层位于第三半导体芯片和第二半导体芯片之间，第三底层填充层位于第四半导体芯片和第三半导体芯片之间。 在一些实施例中，第二底部填充层包括不同于第一和第三底部填充层的材料。

公开(公告)号：US10446525B2

公开(公告)日：2019-10-15

申请号：US16050341

申请日：2018-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-won Choi ,  Won-keun Kim ,  Myung-sung Kang ,  Gwang-sun Seo

IPC: H01L23/52 ,  H01L25/065 ,  H01L21/56

Abstract: A semiconductor package includes a first semiconductor chip including a first through-silicon via (TSV), a second semiconductor chip stacked on the first semiconductor chip and including a second TSV, and a non-conductive film formed between the first semiconductor chip and the second semiconductor chip. The non-conductive film includes two layers having different viscosities.

公开(公告)号：US10797021B2

公开(公告)日：2020-10-06

申请号：US16382376

申请日：2019-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-keun Kim ,  Kyung-suk Oh ,  Ji-han Ko ,  Kil-soo Kim ,  Yeong-seok Kim ,  Joung-phil Lee ,  Hwa-il Jin ,  Su-jung Hyung

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/552 ,  H01L25/00

Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.