公开(公告)号：US20180350675A1

公开(公告)日：2018-12-06

申请号：US16050168

申请日：2018-07-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Hao Chung ,  Chang-Sheng Lin ,  Kuo-Feng Huang ,  Li-Chieh Wu ,  Chun-Chieh Lin

IPC分类号： H01L21/768 ,  H01L23/535

CPC分类号： H01L21/76883 ,  H01L21/02074 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/535

摘要： A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.

公开(公告)号：US20180350625A1

公开(公告)日：2018-12-06

申请号：US16049138

申请日：2018-07-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yuan-Shun CHAO ,  Chih-Wei KUO

IPC分类号： H01L21/44 ,  H01L29/78 ,  H01L21/285 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/26

CPC分类号： H01L21/44 ,  H01L21/28518 ,  H01L29/0847 ,  H01L29/26 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/66969 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

摘要： A semiconductor device includes an isolation insulating layer disposed over a substrate, a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer, a gate structure disposed over a part of the fin structure, the gate structure extending in a second direction crossing the first direction, and a source/drain structure formed on the upper portion of the fin structure, which is not covered by the gate structure and exposed from the isolation insulating layer. The source/drain structure includes a SiP layer, and an upper portion of the source/drain structure includes an alloy layer of Si, Ge and Ti.

公开(公告)号：US20180342455A1

公开(公告)日：2018-11-29

申请号：US15605204

申请日：2017-05-25

申请人： SANDISK TECHNOLOGIES LLC

发明人： Yosuke NOSHO ,  Han-Min KIM

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/768 ,  H01L21/285

CPC分类号： H01L23/528 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76889 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/53295 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor structure includes a semiconductor device located over a substrate, a dielectric layer stack of at least one first dielectric material layer, a silicon nitride layer, and at least one second dielectric material layer overlying the semiconductor device, and interconnect structures including metallic lines and metallic vias and embedded within the dielectric layer stack. The interconnect structures also include a metal silicide portion that directly contacts the silicon nitride layer. A combination of the silicon nitride layer and the metal silicide portion provides a continuous hydrogen barrier structure that is vertically spaced from the top surface of the semiconductor device.

公开(公告)号：US20180331207A1

公开(公告)日：2018-11-15

申请号：US16031210

申请日：2018-07-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Alan B. BOTULA ,  Max L. LIFSON ,  James A. SLINKMAN ,  Theodore G. VAN KESSEL ,  Randy L. WOLF

IPC分类号： H01L29/732 ,  H01L29/78 ,  H01L21/02 ,  B82Y10/00 ,  H01L29/45 ,  H01L29/417 ,  H01L29/41 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L49/02 ,  H01L23/525 ,  H01L23/373 ,  H01L23/367 ,  H01L21/762 ,  H01L21/48 ,  H01L21/3205 ,  H01L21/288 ,  H01L21/285 ,  H01L23/48 ,  H01L23/485

CPC分类号： H01L29/732 ,  B82Y10/00 ,  H01L21/02112 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02271 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02603 ,  H01L21/02628 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/4882 ,  H01L21/7624 ,  H01L23/3677 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5256 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/413 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/456 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer

公开(公告)号：US20180315609A1

公开(公告)日：2018-11-01

申请号：US15963451

申请日：2018-04-26

申请人： Applied Materials, Inc.

发明人： Bencherki Mebarki ,  Xianmin Tang ,  Sundar Ramamurthy ,  Jerome Machillot

IPC分类号： H01L21/285 ,  H01L21/324

CPC分类号： H01L21/28518 ,  H01L21/2855 ,  H01L21/324

摘要： Methods for forming a metal silicide film with low resistivity at low temperature are described. A metal silicide film is formed on a substrate surface and annealed at high pressure and low temperature.

公开(公告)号：US20180261678A1

公开(公告)日：2018-09-13

申请号：US15978546

申请日：2018-05-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Yi LEE ,  Cheng-Yen TSAI ,  Da-Yuan LEE

IPC分类号： H01L29/49 ,  H01L21/285 ,  H01L21/28 ,  H01L21/67 ,  H01L27/088 ,  H01L29/51

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/67167 ,  H01L27/0886 ,  H01L29/517 ,  H01L29/518

摘要： A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. The work-function metal layer has a first thickness. A pre-treatment process of the work-function metal layer may then performed, where the pre-treatment process removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. The treated work-function metal layer has a second thickness less than the first thickness. In various embodiments, after performing the pre-treatment process, another metal layer is deposited over the treated work-function metal layer.

公开(公告)号：US20180254188A1

公开(公告)日：2018-09-06

申请号：US15969137

申请日：2018-05-02

申请人： Samsung Electronics Co., Ltd.

发明人： Yoon-Hae KIM ,  Hwa-sung RHEE ,  Keun-hwi CHO

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L27/088

CPC分类号： H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device includes a gate structure extending in a second direction on a substrate, a source/drain layer disposed on a portion of the substrate adjacent the gate structure in a first direction crossing the second direction, a first conductive contact plug on the gate structure, and a second contact plug structure disposed on the source/drain layer. The second contact plug structure includes a second conductive contact plug and an insulation pattern, and the second conductive contact plug and the insulation pattern are disposed in the second direction and contact each other. The first conductive contact plug and the insulation pattern are adjacent to each other in the first direction. The first and second conductive contact plugs are spaced apart from each other.

公开(公告)号：US20180251894A1

公开(公告)日：2018-09-06

申请号：US15901075

申请日：2018-02-21

申请人： TOKYO ELECTRON LIMITED

发明人： Katsumasa YAMAGUCHI ,  Kensaku NARUSHIMA ,  Hironori YAGI ,  Kouichi SEKIDO

IPC分类号： C23C16/455 ,  H01L21/285 ,  C23C16/14

CPC分类号： C23C16/45527 ,  C23C16/14 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/32051

摘要： A gas supply device for vaporizing a raw material inside a raw material container and supplying a raw material gas into a processing container together with a carrier gas, which includes: a buffer tank provided between the raw material container and the processing container; an Evac line for exhausting interiors of the buffer tank and the raw material container; a memory part that stores a first internal pressure of the buffer tank when a process is performed by supplying the raw material gas into the processing container; and a control part configured to control a flow rate of a gas exhausted to the Evac line and a flow rate of the raw material gas and the carrier gas filled in the buffer tank, so that a second internal pressure of the buffer tank becomes equal to the first internal pressure before supplying the raw material gas into the processing container.

公开(公告)号：US20180240875A1

公开(公告)日：2018-08-23

申请号：US15954300

申请日：2018-04-16

申请人： International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

发明人： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Chun-chen Yeh

IPC分类号： H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L29/0847 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

摘要： Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.

公开(公告)号：US20180197781A1

公开(公告)日：2018-07-12

申请号：US15911709

申请日：2018-03-05

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Pascal Chevalier ,  Gregory Avenier

IPC分类号： H01L21/8228 ,  H01L29/06 ,  H01L27/102 ,  H01L21/311 ,  H01L21/285 ,  H01L21/02 ,  H01L21/265 ,  H01L21/761

CPC分类号： H01L21/82285 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/761 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L27/1022 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/42304 ,  H01L29/66272 ,  H01L29/732

摘要： A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.