公开(公告)号：US20200035838A1

公开(公告)日：2020-01-30

申请号：US16591458

申请日：2019-10-02

Applicant: Samsung Electronics Co., Ltd. ,  Board of Regents, The University of Texas System

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Robert M. Wallace ,  Xiaoye Qin

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/04

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a substrate having a source region, a drain region, and a channel region between the source region and the drain region, the substrate having an epitaxial III-V material that includes three elements thereon, a source electrode over the source region, a drain electrode over the drain region, and a crystalline oxide layer including an oxide formed on the epitaxial III-V material in the channel region, the epitaxial III-V material including three elements.

公开(公告)号：US10475930B2

公开(公告)日：2019-11-12

申请号：US15359480

申请日：2016-11-22

Applicant: Samsung Electronics Co., Ltd. ,  Board of Regents, The University of Texas System

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Robert M. Wallace ,  Xiaoye Qin

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L21/02 ,  H01L29/04

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a substrate having a source region, a drain region, and a channel region between the source region and the drain region, the substrate having an epitaxial III-V material that includes three elements thereon, a source electrode over the source region, a drain electrode over the drain region, and a crystalline oxide layer including an oxide formed on the epitaxial III-V material in the channel region, the epitaxial III-V material including three elements.

公开(公告)号：US20190181140A1

公开(公告)日：2019-06-13

申请号：US15977949

申请日：2018-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Dharmendar Palle ,  Rwik Sengupta ,  Mohammad Ali Pourghaderi

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: A CMOS system on chip including a series of partial gate-all-around field effect transistors. Each partial GAA FET includes a fin having a stack of channel regions, source and drain regions on opposite sides of the fin, a dielectric separation region including a dielectric material between first and second channel regions, a gate stack on the fin, and a pair of sidewall spacers on opposite sides of the gate stack. A portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of a respective sidewall spacer. The length of the portion of the dielectric separation region of one of the partial GAA FETs is different than the length of the portion of the dielectric separation region of another one of the partial GAA FETs.

公开(公告)号：US20190148312A1

公开(公告)日：2019-05-16

申请号：US15927239

申请日：2018-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Harsono S. Simka ,  Ganesh Hegde ,  Joon Goo Hong ,  Rwik Sengupta ,  Mark S. Rodder

IPC: H01L23/00 ,  H01L23/522 ,  H01L27/02 ,  H04L9/32

CPC classification number: H01L23/573 ,  G09C1/00 ,  H01L23/5228 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L27/0207 ,  H04L9/3278

Abstract: A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. The variable conductivity layer is conductive for a first portion of the connective components connected to a first portion of the circuit elements. The variable conductivity layer is insulating for a second portion of the connective components connected to a second portion of the circuit elements. Thus, the first portion of the circuit elements are active and the second portion of the circuit elements are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry may be indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.

公开(公告)号：US20180269152A1

公开(公告)日：2018-09-20

申请号：US15681243

申请日：2017-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Andrew Paul Hoover ,  Matthew Berzins ,  Sam Tower ,  Mark S. Rodder

IPC: H01L23/528 ,  H01L27/02 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L21/321

Abstract: A semiconductor integrated circuit including a substrate, a series of metal layers, and a series of insulating layers. The metal layers and the insulating layers are alternately arranged in a stack on the substrate. The semiconductor integrated circuit also includes at least two standard cells in the substrate and at least one power rail crossing over boundaries of the at least two standard cells. The power rail includes a vertical section of conductive material extending continuously through at least two vertical levels of the stack. The two vertical levels of the stack include one metal layer and one insulating layer. The insulating layer is above the metal layer.

公开(公告)号：US10026751B2

公开(公告)日：2018-07-17

申请号：US15210867

申请日：2016-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Rwik Sengupta ,  Wei-E Wang ,  Ryan Hatcher ,  Mark S. Rodder

IPC: H01L27/01 ,  H01L27/12 ,  H01L23/522 ,  H01L23/528 ,  H01L29/24 ,  H01L29/45 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/84 ,  H01L29/10

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include one or more transition metal dichalcogenide materials such as MoS2, WS2, WSe2, and/or combinations thereof.

公开(公告)号：US09978833B2

公开(公告)日：2018-05-22

申请号：US15289951

申请日：2016-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Joon Goo Hong ,  Dharmendar Reddy Palle ,  Mark S. Rodder

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/84

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/786

Abstract: A semiconductor device and a method to form the semiconductor device are disclosed. An n-channel component of the semiconductor device includes a first horizontal nanosheet (hNS) stack and a p-channel component includes a second hNS stack. The first hNS stack includes a first gate structure having a plurality of first gate layers and at least one first channel layer. A first internal spacer is disposed between at least one first gate layer and a first source/drain structure in which the first internal spacer has a first length. The second hNS stack includes a second gate structure having a plurality of second gate layers and at least one second channel layer. A second internal spacer is disposed between at least one second gate layer and a second source/drain structure in which the second internal spacer has a second length that is greater than the first length.

公开(公告)号：US20180130785A1

公开(公告)日：2018-05-10

申请号：US15442592

申请日：2017-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Titash Rakshit ,  Borna J. Obradovic ,  Chris Bowen ,  Mark S. Rodder

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/04 ,  H01L29/16 ,  H01L23/532 ,  H01L29/47 ,  H01L23/522 ,  H01L21/02 ,  H01L21/28 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/311 ,  H01L27/12 ,  H01L27/092 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L27/0207 ,  H01L21/02068 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/02236 ,  H01L21/02244 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/04 ,  H01L29/16 ,  H01L29/47 ,  H01L29/665

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.

公开(公告)号：US20180114727A1

公开(公告)日：2018-04-26

申请号：US15818657

申请日：2017-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong ,  Seung Hun Lee ,  Pan Kwi Park ,  Seung Ryul Lee

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L21/823807 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/04 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

Abstract: A CMOS circuit includes a partial GAA nFET and a partial GAA pFET. The nFET and the pFET each include a fin including a stack of nanowire-like channel regions and a dielectric separation region extending completely between first and second nanowire-like channel regions of the stack. The nFET and the pFET each also include a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer does not extend between the first and second nanowire-like channel regions. The channel heights of the nanowire-like channel regions of the partial GAA nFET and the partial GAA pFET are different.

公开(公告)号：US09941405B2

公开(公告)日：2018-04-10

申请号：US15340951

申请日：2016-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Wei-E Wang ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L21/306 ,  H01L21/3205 ,  H01L29/06 ,  H01L29/417 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L29/165 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L21/30604 ,  H01L21/32055 ,  H01L21/32133 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618

Abstract: A method of manufacturing a nanosheet or nanowire device from a stack including an alternating arrangement of sacrificial layers and channel layers on a substrate. The method includes deep etching portions of the stack to form electrode recesses for a source electrode and a drain electrode, forming conductive passivation layers in the electrode recesses, and epitaxially growing the source and drain electrodes in the electrode recesses. Each conductive passivation layer extends at least partially along a side of one of the electrode recesses. Portions of the substrate at lower ends of the electrode recesses are uncovered by the conductive passivation layers. The source and drain electrodes are grown from the substrate and the conductive passivation layers substantially inhibit the source and drain electrodes from being grown from the channel layers.