知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.015 seconds)

    Methods to achieve strained channel finFET devices
    1.
    发明授权
    Methods to achieve strained channel finFET devices 有权

    公开(公告)号：US10205025B2

    公开(公告)日：2019-02-12

    申请号：US15276779

    申请日：2016-09-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jorge A. Kittl ,  Joon Goo Hong ,  Dharmendar Reddy Palle ,  Mark S. Rodder

    IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

    Abstract: Methods to achieve strained channel finFET devices and resulting finFET devices are presented. In an embodiment, a method for processing a field effect transistor (FET) device may include forming a fin structure comprising a fin channel on a substrate. The method may also include forming a sacrificial epitaxial layer on a side of the fin structure. Additionally, the method may include forming a deep recess in a region that includes at least a portion of the fin structure, wherein the fin structure and sacrificial layer relax to form a strain on the fin channel. The method may also include depositing source/drain (SD) material in the deep recess to preserve the strain on the fin channel.

    Integrated circuit chips having field effect transistors with different gate designs
    2.
    发明授权
    Integrated circuit chips having field effect transistors with different gate designs 有权
    具有不同栅极设计的场效应晶体管的集成电路芯片

    公开(公告)号：US09425275B2

    公开(公告)日：2016-08-23

    申请号：US14728104

    申请日：2015-06-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mark S. Rodder ,  Dharmendar Reddy Palle ,  Borna J. Obradovic

    IPC: H01L27/088 ,  H01L29/423 ,  H01L21/8234

    CPC classification number: H01L29/4238 ,  H01L21/823431 ,  H01L21/823456 ,  H01L27/0886

    Abstract: An integrated circuit chip includes a semiconductor substrate, a first back-end-of-line unit circuit that includes a first group of field effect transistors, a second gate-loaded unit circuit that includes a second group of field effect transistors. The first group of field effect transistors includes a first transistor and the second group of field effect transistors includes a second transistor. A bottom surface of a gate electrode of the first transistor extends closer to a bottom surface of the semiconductor substrate than does a bottom surface of a gate electrode of the second transistor.

    Abstract translation: 集成电路芯片包括半导体衬底，第一后端线单元电路，其包括第一组场效应晶体管，第二栅极负载单元电路，其包括第二组场效应晶体管。 第一组场效应晶体管包括第一晶体管，第二组场效应晶体管包括第二晶体管。 与第二晶体管的栅电极的底表面相比，第一晶体管的栅电极的底表面比半导体衬底的底表面更靠近。

    INTEGRATED CIRCUIT DEVICES INCLUDING CONTACTS AND METHODS OF FORMING THE SAME
    3.
    发明申请
    INTEGRATED CIRCUIT DEVICES INCLUDING CONTACTS AND METHODS OF FORMING THE SAME 有权
    包括联系人的集成电路设备及其形成方法

    公开(公告)号：US20150243747A1

    公开(公告)日：2015-08-27

    申请号：US14628541

    申请日：2015-02-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jorge A. Kittl ,  Dharmendar Reddy Palle ,  Mark S. Rodder

    IPC: H01L29/417 ,  H01L29/45 ,  H01L27/088 ,  H01L29/78

    CPC classification number: H01L29/41791 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/45 ,  H01L29/7848 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated circuit devices including contacts and methods of forming the same are provided. The devices may include a fin on a substrate, a gate structure on the fin and a source/drain region in the fin at a side of the gate structure. The devices may further include a contact plug covering an uppermost surface of the source/drain region and a sidewall of the gate structure. The contact plug may include an inner portion including a first material and an outer portion including a second material different from the first material. The outer portion may at least partially cover a sidewall of the inner portion, and a portion of the outer portion may be disposed between the sidewall of the gate structure and the sidewall of the inner portion.

    Abstract translation: 提供了包括触点的集成电路装置及其形成方法。 器件可以包括衬底上的翅片，翅片上的栅极结构和栅极结构侧的鳍中的源极/漏极区域。 所述装置还可以包括覆盖源极/漏极区域的最上表面和栅极结构的侧壁的接触插塞。 接触插塞可以包括包括第一材料的内部部分和包括不同于第一材料的第二材料的外部部分。 外部部分可以至少部分地覆盖内部部分的侧壁，并且外部部分的一部分可以设置在门结构的侧壁和内部部分的侧壁之间。

    Integrated circuit devices including contacts and methods of forming the same
    6.
    发明授权
    Integrated circuit devices including contacts and methods of forming the same 有权
    集成电路器件，包括触点及其形成方法

    公开(公告)号：US09431492B2

    公开(公告)日：2016-08-30

    申请号：US14628541

    申请日：2015-02-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jorge A. Kittl ,  Dharmendar Reddy Palle ,  Mark S. Rodder

    IPC: H01L29/45 ,  H01L29/417 ,  H01L27/088 ,  H01L29/78 ,  H01L27/12 ,  H01L21/768 ,  H01L23/485

    CPC classification number: H01L29/41791 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/45 ,  H01L29/7848 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated circuit devices including contacts and methods of forming the same are provided. The devices may include a fin on a substrate, a gate structure on the fin and a source/drain region in the fin at a side of the gate structure. The devices may further include a contact plug covering an uppermost surface of the source/drain region and a sidewall of the gate structure. The contact plug may include an inner portion including a first material and an outer portion including a second material different from the first material. The outer portion may at least partially cover a sidewall of the inner portion, and a portion of the outer portion may be disposed between the sidewall of the gate structure and the sidewall of the inner portion.

    Abstract translation: 提供了包括触点的集成电路装置及其形成方法。 器件可以包括衬底上的翅片，翅片上的栅极结构和栅极结构侧的鳍中的源极/漏极区域。 所述装置还可以包括覆盖源极/漏极区域的最上表面和栅极结构的侧壁的接触插塞。 接触插塞可以包括包括第一材料的内部部分和包括不同于第一材料的第二材料的外部部分。 外部部分可以至少部分地覆盖内部部分的侧壁，并且外部部分的一部分可以设置在门结构的侧壁和内部部分的侧壁之间。

Patent Agency Ranking