知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

51 records (took 0.054 seconds)

    Method Of Operating FET Low Current 3D Re-Ram
    41.
    发明申请
    Method Of Operating FET Low Current 3D Re-Ram 有权
    操作FET低电流3D Re-Ram的方法

    公开(公告)号：US20150170742A1

    公开(公告)日：2015-06-18

    申请号：US14591546

    申请日：2015-01-07

    Applicant: SanDisk 3D LLC

    Inventor： Abhijit Bandyopadhyay ,  Roy E. Scheuerlein ,  Chandrasekhar R. Gorla ,  Brian Le

    IPC: G11C13/00 ,  G11C16/34

    CPC classification number: G11C13/0069 ,  G11C7/00 ,  G11C11/5614 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C16/3454 ,  G11C2013/0083 ,  G11C2213/71 ,  G11C2213/78 ,  G11C2213/79

    Abstract: Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.

    Abstract translation: 本文公开了操作ReRAM存储器。 可以在最初对它们进行编程之前训练存储器单元。 训练可能有助于建立渗透路径。 在某些方面，当训练和编程时，晶体管限制存储器单元的电流。 在训练期间使用更高的电流限制，这调节存储器单元以进行更好的编程。 非存储器可以在单极模式下操作。 存储器单元可以存储每个存储器单元的多个位。 可以将存储器单元从其当前状态直接设置为一个至少两个数据状态。 存储单元可以直接复位到具有下一个最高电阻的状态。 诸如脉冲宽度和/或幅度的程序条件可以取决于存储器单元被设置到的状态。 较高的能量可用于编程更高的电流状态。

    Temperature compensation of conductive bridge memory arrays
    43.
    发明授权
    Temperature compensation of conductive bridge memory arrays 有权
    导电桥式存储器阵列的温度补偿

    公开(公告)号：US09047983B2

    公开(公告)日：2015-06-02

    申请号：US14256925

    申请日：2014-04-19

    Applicant: SANDISK 3D LLC

    Inventor： Roy E. Scheuerlein ,  George Samachisa

    IPC: G11C7/04 ,  G11C7/00 ,  G11C5/06 ,  G11C11/56 ,  G11C7/12 ,  G11C8/08 ,  G11C16/34 ,  G11C29/02 ,  G11C13/00 ,  G11C5/14 ,  G11C5/02 ,  G11C29/12

    CPC classification number: G11C11/5642 ,  G11C5/02 ,  G11C5/063 ,  G11C5/14 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0035 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2213/71 ,  G11C2213/77

    Abstract: Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.

    Abstract translation: 描述了用于操作包括基于与半导体存储器阵列相关联的一个或多个阵列条件动态调整控制线电压（例如，未选择的字线或未选择的位线电压）的半导体存储器阵列的方法。 一个或多个阵列条件可以包括与半导体存储器阵列相关联的温度或与半导体存储器阵列相关联的特定数量的写入周期。 在一些实施例中，基于一个或多个阵列条件产生中间电压并施加到半导体存储器阵列的未选字线和未选位线。 可以产生一个或多个中间电压，使得共享所选字线的未选择的存储单元之间的第一电压差与基于一个或多个阵列条件共享所选位线的其他未选择的存储器单元之间的第二电压差不同。

    METHOD OF OPERATING FET LOW CURRENT 3D RE-RAM
    44.
    发明申请
    METHOD OF OPERATING FET LOW CURRENT 3D RE-RAM 有权
    操作FET低电流3D再现RAM的方法

    公开(公告)号：US20150070966A1

    公开(公告)日：2015-03-12

    申请号：US14025442

    申请日：2013-09-12

    Applicant: SanDisk 3D LLC

    Inventor： Abhijit Bandyopadhyay ,  Roy E. Scheuerlein ,  Chandrasekhar R. Gorla ,  Brian Le

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C7/00 ,  G11C11/5614 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C16/3454 ,  G11C2013/0083 ,  G11C2213/71 ,  G11C2213/78 ,  G11C2213/79

    Abstract: Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.

    Abstract translation: 本文公开了操作ReRAM存储器。 可以在最初对它们进行编程之前训练存储器单元。 训练可能有助于建立渗透路径。 在某些方面，当训练和编程时，晶体管限制存储器单元的电流。 在训练期间使用更高的电流限制，这调节存储器单元以进行更好的编程。 非存储器可以在单极模式下操作。 存储器单元可以存储每个存储器单元的多个位。 可以将存储器单元从其当前状态直接设置为一个至少两个数据状态。 存储单元可以直接复位到具有下一个最高电阻的状态。 诸如脉冲宽度和/或幅度的程序条件可以取决于存储器单元被设置到的状态。 较高的能量可用于编程更高的电流状态。

    Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning
    45.
    发明授权
    Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning 有权
    用于三维矩阵阵列存储器布局的方法和装置，用于降低成本图案化

    公开(公告)号：US08969923B2

    公开(公告)日：2015-03-03

    申请号：US14334653

    申请日：2014-07-17

    Applicant: SanDisk 3D LLC

    Inventor： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

    IPC: H01L23/52 ,  G11C5/06

    CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

    Abstract: Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.

    Abstract translation: 为三维存储器的存储器层布局提供了装置，方法和系统。 存储层包括多个存储器阵列块; 耦合到其上的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。 存储器线从存储器阵列块延伸，使用侧壁限定的工艺形成，并且半间距尺寸小于用于形成存储器线的光刻工具的标称最小特征尺寸能力。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。 存储线被布置成允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供在其它存储器线路之间的区域的图案。 公开其他方面。

    TEMPERATURE COMPENSATION OF CONDUCTIVE BRIDGE MEMORY ARRAYS
    47.
    发明申请
    TEMPERATURE COMPENSATION OF CONDUCTIVE BRIDGE MEMORY ARRAYS 有权
    导电桥记忆阵列的温度补偿

    公开(公告)号：US20140226393A1

    公开(公告)日：2014-08-14

    申请号：US14256925

    申请日：2014-04-19

    Applicant: SANDISK 3D LLC

    Inventor： Roy E. Scheuerlein ,  George Samachisa

    IPC: G11C13/00

    CPC classification number: G11C11/5642 ,  G11C5/02 ,  G11C5/063 ,  G11C5/14 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0035 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2213/71 ,  G11C2213/77

    Abstract: Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.

    Abstract translation: 描述了用于操作包括基于与半导体存储器阵列相关联的一个或多个阵列条件动态调整控制线电压（例如，未选择的字线或未选择的位线电压）的半导体存储器阵列的方法。 一个或多个阵列条件可以包括与半导体存储器阵列相关联的温度或与半导体存储器阵列相关联的特定数量的写周期。 在一些实施例中，基于一个或多个阵列条件产生中间电压并施加到半导体存储器阵列的未选字线和未选位线。 可以产生一个或多个中间电压，使得共享所选字线的未选择的存储单元之间的第一电压差与基于一个或多个阵列条件共享所选位线的其他未选择的存储器单元之间的第二电压差不同。

    3D MEMORY HAVING VERTICAL SWITCHES WITH SURROUND GATES AND METHOD THEREOF
    50.
    发明申请
    3D MEMORY HAVING VERTICAL SWITCHES WITH SURROUND GATES AND METHOD THEREOF 审中-公开
    具有环形门的垂直开关的3D存储器及其方法

    公开(公告)号：US20130336037A1

    公开(公告)日：2013-12-19

    申请号：US13838782

    申请日：2013-03-15

    Applicant: SANDISK 3D LLC

    Inventor： Yung-Tin Chen ,  Steven J. Radigan ,  Roy E. Scheuerlein ,  Raul Adrian Cernea

    IPC: G11C5/06 ,  H01L27/105

    CPC classification number: H01L27/249 ,  G06F12/0238 ,  G11C5/025 ,  G11C5/06 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/71 ,  H01L21/76877 ,  H01L27/1052 ,  H01L27/2454 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

    Abstract: A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs.

    Abstract translation: 3D存储器件的垂直切换层用于将一组垂直局部位线切换到相应的全局位线集合，垂直切换层是垂直薄膜晶体管（TFT）的TFT通道的2D阵列，其与 连接到本地位线阵列，每个TFT将局部位线切换到相应的全局位线。 阵列中的TFT分别具有沿着x轴和y轴的长度Lx和Ly的间隔，使得栅极材料层在xy平面内围绕每个TFT形成环绕栅，并且具有合并以形成行选择的厚度 沿x轴线，同时保持单独行选择线之间的长度Ls的间隔。 环绕栅极提高了TFT的开关容量。

Patent Agency Ranking