公开(公告)号：US09443910B1

公开(公告)日：2016-09-13

申请号：US14795211

申请日：2015-07-09

Applicant: SanDisk 3D LLC

Inventor： Kan Fujiwara ,  Takuya Futase ,  Toshihiro Iizuka ,  Shin Kikuchi ,  Yoichiro Tanaka ,  Akio Nishida ,  Christopher J Petti

IPC: H01L27/115 ,  H01L27/24 ,  H01L45/00 ,  H01L21/822

CPC classification number: H01L27/2481 ,  H01L21/8221 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: A three-dimensional (3D) non-volatile memory array having a silicide bit line and method of fabricating is disclosed. The fabrication technique may comprise forming a metal silicide for at least a portion of the bit line. The device has reversible resistivity material between the word lines and the bit lines. The reversible resistivity material may be a metal oxide. The metal that is used to form the silicide may serve as an oxygen scavenger to draw oxygen away from the silicon, thus preventing formation of silicon oxide between the reversible resistivity material and the bit line. The metal silicide may also help prevent formation of a depletion layer in silicon in the bit line.

Abstract translation: 公开了一种具有硅化物位线和制造方法的三维（3D）非易失性存储器阵列。 制造技术可以包括为位线的至少一部分形成金属硅化物。 该器件在字线和位线之间具有可逆电阻率材料。 可逆电阻率材料可以是金属氧化物。 用于形成硅化物的金属可以用作氧清除剂，以从氧中吸取氧，从而防止在可逆电阻率材料和位线之间形成氧化硅。 金属硅化物还可以帮助防止在位线中的硅中形成耗尽层。

公开(公告)号：US08969923B2

公开(公告)日：2015-03-03

申请号：US14334653

申请日：2014-07-17

Applicant: SanDisk 3D LLC

Inventor： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

IPC: H01L23/52 ,  G11C5/06

CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

Abstract: Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.

Abstract translation: 为三维存储器的存储器层布局提供了装置，方法和系统。 存储层包括多个存储器阵列块; 耦合到其上的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。 存储器线从存储器阵列块延伸，使用侧壁限定的工艺形成，并且半间距尺寸小于用于形成存储器线的光刻工具的标称最小特征尺寸能力。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。 存储线被布置成允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供在其它存储器线路之间的区域的图案。 公开其他方面。

公开(公告)号：US20170125483A1

公开(公告)日：2017-05-04

申请号：US14928999

申请日：2015-10-30

Applicant: SANDISK 3D LLC

Inventor： Yoichiro Tanaka

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2418 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1683

Abstract: Methods for improving the operation of a memory array by arranging a Metal-Insulator-Metal (MIM) structure between a word line and an adjustable resistance bit line structure are described. The MIM structure may correspond with a metal/ReRAM material/metal structure that is arranged between the word line and an intrinsic polysilicon region of the adjustable resistance bit line structure. In one example, a word line (e.g., TiN) may be arranged adjacent to a ReRAM material (e.g., HfOx) that is adjacent to a first metal (e.g., TiN) that is adjacent to the intrinsic polysilicon region. The first metal may comprise a metal, metal-nitride, or a metal-silicide. In another example, the word line may be arranged adjacent to a ReRAM material that is adjacent to a first metal (e.g., TiN) that is adjacent to a second metal different from the first metal (e.g., tungsten) that is adjacent to the intrinsic polysilicon region.

公开(公告)号：US20140328105A1

公开(公告)日：2014-11-06

申请号：US14334653

申请日：2014-07-17

Applicant: SanDisk 3D LLC

Inventor： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

IPC: G11C5/06

CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

Abstract: Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.

Abstract translation: 为三维存储器的存储器层布局提供了装置，方法和系统。 存储层包括多个存储器阵列块; 耦合到其上的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。 存储器线从存储器阵列块延伸，使用侧壁限定的工艺形成，并且半间距尺寸小于形成存储器线的光刻工具的标称最小特征尺寸能力。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。 存储线被布置成允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供在其它存储器线路之间的区域的图案。 公开其他方面。