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    Parallel bit line three-dimensional resistive random access memory
    1.
    发明授权
    Parallel bit line three-dimensional resistive random access memory 有权

    公开(公告)号：US09698202B2

    公开(公告)日：2017-07-04

    申请号：US14635419

    申请日：2015-03-02

    申请人： SANDISK 3D LLC

    发明人： Seje Takaki

    IPC分类号： H01L27/24 ,  G11C13/00 ,  H01L45/00

    CPC分类号： H01L27/249 ,  G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

    摘要： Resistive random access memory (ReRAM) array includes line stack structures located over a substrate. The line stack structures are laterally spaced apart along a first horizontal direction, and extend along a second horizontal direction that is different from the first horizontal direction. Each line stack structure comprises an alternating plurality of word lines and bit lines. An intervening line stack including a memory material line structure, an intrinsic semiconductor material line structure, and a doped semiconductor material line structure is located between each vertically neighboring pair of a word line and a bit line within the alternating plurality of word lines and bit lines. A two-dimensional array of vertical selector lines functions as gate electrodes that activates a semiconductor channel between a word line and a bit line. Resistance of the memory material line structure contacting the activated semiconductor channel can be programmed and/or measured within the ReRAM array.

    RERAM MIM STRUCTURE FORMATION
    4.
    发明申请
    RERAM MIM STRUCTURE FORMATION 审中-公开

    公开(公告)号：US20170125483A1

    公开(公告)日：2017-05-04

    申请号：US14928999

    申请日：2015-10-30

    申请人： SANDISK 3D LLC

    发明人： Yoichiro Tanaka

    IPC分类号： H01L27/24 ,  H01L45/00

    CPC分类号： H01L27/2418 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1683

    摘要： Methods for improving the operation of a memory array by arranging a Metal-Insulator-Metal (MIM) structure between a word line and an adjustable resistance bit line structure are described. The MIM structure may correspond with a metal/ReRAM material/metal structure that is arranged between the word line and an intrinsic polysilicon region of the adjustable resistance bit line structure. In one example, a word line (e.g., TiN) may be arranged adjacent to a ReRAM material (e.g., HfOx) that is adjacent to a first metal (e.g., TiN) that is adjacent to the intrinsic polysilicon region. The first metal may comprise a metal, metal-nitride, or a metal-silicide. In another example, the word line may be arranged adjacent to a ReRAM material that is adjacent to a first metal (e.g., TiN) that is adjacent to a second metal different from the first metal (e.g., tungsten) that is adjacent to the intrinsic polysilicon region.

    THREE-DIMENSIONAL RESISTIVE RANDOM ACCESS MEMORY CONTAINING SELF-ALIGNED MEMORY ELEMENTS
    6.
    发明申请
    THREE-DIMENSIONAL RESISTIVE RANDOM ACCESS MEMORY CONTAINING SELF-ALIGNED MEMORY ELEMENTS 审中-公开
    包含自对准存储元件的三维电阻随机存取存储器

    公开(公告)号：US20170077184A1

    公开(公告)日：2017-03-16

    申请号：US14851296

    申请日：2015-09-11

    申请人： SanDisk 3D LLC

    发明人： Shin KIKUCHI ,  Kazushi KOMEDA ,  Takuya FUTASE ,  Teruyuki MINE ,  Seje TAKAKI ,  Eiji HAYASHI ,  Toshihide TOBITSUKA

    IPC分类号： H01L27/24 ,  H01L45/00

    CPC分类号： H01L27/2481 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633

    摘要： An alternating material stack of insulator lines and first electrically conductive material layers is formed over a substrate, and is patterned to provide alternating stacks of insulating layers and first electrically conductive lines. A metal can be selectively deposited on the physically exposed sidewalls of the first electrically conductive material layers to form metal lines, while not growing from the surfaces of the insulator lines. The metal lines are oxidized to form metal oxide lines that are self-aligned to the sidewalls of the first electrically conductive lines. Vertically extending second electrically conductive lines can be formed as a two-dimensional array of generally pillar-shaped structures between the alternating stacks of the insulator lines and the first electrically conductive lines. Each portion of the metal oxide lines at junctions of first and second electrically conductive lines constitute a resistive memory element for a resistive random access memory (ReRAM) device.

    摘要翻译： 绝缘体线和第一导电材料层的交替材料堆叠形成在衬底上，并被图案化以提供绝缘层和第一导电线的交替堆叠。 可以在第一导电材料层的物理暴露的侧壁上选择性地沉积金属以形成金属线，而不会从绝缘体线的表面生长。 金属线被氧化以形成与第一导电线的侧壁自对准的金属氧化物线。 垂直延伸的第二导电线可以形成为在绝缘体线的交替堆叠和第一导电线之间的大致柱状结构的二维阵列。 金属氧化物线在第一和第二导电线的交点处的每个部分构成用于电阻随机存取存储器（ReRAM）器件的电阻性存储元件。

    Multiple layer forming scheme for vertical cross point reram
    9.
    发明授权
    Multiple layer forming scheme for vertical cross point reram 有权
    垂直交叉点多层形成方案

    公开(公告)号：US09543009B2

    公开(公告)日：2017-01-10

    申请号：US14887532

    申请日：2015-10-20

    申请人： SanDisk 3D LLC

    发明人： Chang Siau ,  Tianhong Yan

    IPC分类号： G11C13/00

    CPC分类号： G11C13/0069 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/77

    摘要： Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, during a forming operation, a cross-point memory array may be biased such that waste currents are minimized or eliminated. In one example, the memory array may be biased such that a first word line comb is set to a first voltage, a second word line comb interdigitated with the first word line comb is set to the first voltage, and selected vertical bit lines are set to a second voltage such that a forming voltage is applied across non-volatile storage elements to be formed. In some embodiments, a memory array may include a plurality of word line comb layers and a forming operation may be concurrently performed on non-volatile storage elements on all of the plurality of word line comb layers or a subset of the plurality of word line comb layers.

    摘要翻译： 描述了在非易失性存储系统中形成非易失性存储元件的方法。 在一些实施例中，在成形操作期间，可以偏置交叉点存储器阵列，使得浪费电流被最小化或消除。 在一个示例中，存储器阵列可以被偏置，使得第一字线梳被设置为第一电压，与第一字线梳交织的第二字线梳被设置为第一电压，并且选择的垂直位线被设置 到第二电压，使得在要形成的非易失性存储元件上施加形成电压。 在一些实施例中，存储器阵列可以包括多个字线梳状层，并且可以在所有多个字线梳状层上的非易失性存储元件上同时执行形成操作，或者多个字线梳的子集 层。

    Multilevel contact to a 3D memory array and method of making thereof
    10.
    发明授权
    Multilevel contact to a 3D memory array and method of making thereof 有权
    与3D存储器阵列的多层接触及其制造方法

    公开(公告)号：US09515023B2

    公开(公告)日：2016-12-06

    申请号：US14643211

    申请日：2015-03-10

    申请人： SANDISK 3D LLC

    发明人： Toshihide Tobitsuka ,  Seje Takaki

    IPC分类号： H01L23/535 ,  H01L21/768 ,  H01L27/115 ,  H01L27/24

    CPC分类号： H01L23/535 ,  H01L21/76895 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481 ,  H01L27/249 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A multi-level device includes at least one device region and at least one contact region. The contact region has a stack of alternating plurality of electrically conductive layers and plurality of electrically insulating layers located over a substrate. The plurality of electrically conductive layers form a stepped pattern in the contact region, where each respective electrically insulating layer includes a sidewall and a respective underlying electrically conductive layer in the stack extends laterally beyond the sidewall. Optionally, a plurality of electrically conductive via connections can be formed, which have top surfaces within a same horizontal plane, have bottom surfaces contacting a respective electrically conductive layer located at different levels, and are isolated from one another by at least one trench isolation structure.

    摘要翻译： 多级设备包括至少一个设备区域和至少一个接触区域。 接触区域具有交替的多个导电层和位于衬底上方的多个电绝缘层的堆叠。 多个导电层在接触区域中形成阶梯图案，其中每个相应的电绝缘层包括侧壁，并且堆叠中的相应的下面的导电层横向延伸超过侧壁。 可选地，可以形成多个导电通孔连接件，其具有在相同水平平面内的顶表面，其底表面接触位于不同水平的相应导电层，并且通过至少一个沟槽隔离结构彼此隔离 。