公开(公告)号：US09653617B2

公开(公告)日：2017-05-16

申请号：US14723038

申请日：2015-05-27

Applicant: SanDisk 3D LLC

Inventor： Guangle Zhou ,  Ming-Che Wu ,  Yung-Tin Chen

IPC: H01L29/786 ,  H01L27/24 ,  H01L29/423 ,  H01L29/66 ,  H01L21/265 ,  H01L45/00

CPC classification number: H01L29/78696 ,  H01L21/26513 ,  H01L21/2652 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78642 ,  H01L45/16

Abstract: A multiple junction thin film transistor (TFT) is disclosed. The body of the TFT may have an n+ layer residing in a p− region of the body. The TFT may have an n+ source and an n+ drain on either side of the p− region of the body. Thus, the TFT has an n+/p−/n+/p−/n+ structure in this example. The n+ layer in the p− region increases the breakdown voltage. Also, drive current is increased. The impurity concentration in the n+ layer in the p− body and/or thickness of the n+ layer in the p− body may be tuned to increase performance of the TFT. In an alternative, the body of the TFT has a p+ layer residing in an n− region of the body. The TFT may have a p+ source and a p+ drain on either side of the p− region of the body.

公开(公告)号：US09230985B1

公开(公告)日：2016-01-05

申请号：US14515054

申请日：2014-10-15

Applicant: SanDisk 3D LLC

Inventor： Ming-Che Wu ,  Peter Rabkin ,  Tim Chen

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/786 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L29/0895 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78642

Abstract: A vertically oriented thin film transistor (TFT) having a tunnel barrier is disclosed. The tunnel barrier may be formed from a dielectric such as silicon oxide or hafnium oxide. The vertically oriented TFT selection device with tunnel barrier may serve as a selection device in a 3D memory array. The vertically oriented TFT may be used to connect/disconnect a global bit line to/from a vertical bit line in a 3D memory array. The vertically oriented TFT may be used to connect/disconnect a source line to/from a channel of a vertical NAND string in a 3D memory array. A vertical TFT with tunnel barrier has a high breakdown voltage, low leakage current, and high on current. The tunnel barrier can be at the top junction or bottom junction of the TFT.

Abstract translation: 公开了一种具有隧道势垒的垂直取向薄膜晶体管（TFT）。 隧道势垒可以由诸如氧化硅或氧化铪的电介质形成。 具有隧道势垒的垂直取向的TFT选择装置可以用作3D存储器阵列中的选择装置。 可以使用垂直取向的TFT来连接/断开与3D存储器阵列中的垂直位线的全局位线。 垂直取向的TFT可以用于将源极线连接到/离开3D存储器阵列中的垂直NAND串的通道。 具有隧道势垒的垂直TFT具有高击穿电压，低漏电流和高导通电流。 隧道势垒可以在TFT的顶部结或底部结。

公开(公告)号：US20160111517A1

公开(公告)日：2016-04-21

申请号：US14519068

申请日：2014-10-20

Applicant: SANDISK 3D LLC

Inventor： Wei-Te Wu ,  Ming-Che Wu ,  Yung-Tin Chen

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L27/115 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L29/6675 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31111 ,  H01L21/823885 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/78648 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/141 ,  H01L45/146 ,  H01L45/16

Abstract: Methods for forming a dual gate structure for a vertical TFT are described. The dual gate structure may be formed by performing a first etching process that includes forming a first set of trenches by etching a first set of oxide pillars to a first depth and forming a second set of trenches by etching a second set of oxide pillars to a second depth higher than the first depth, forming a first set of gate structures within the first set of trenches, forming a second set of gate structures within the second set of trenches, performing a second etching process that includes forming a third set of trenches by etching the first set of gate structures from a second initial depth to a third depth and forming a fourth set of trenches by etching the second set of gate structures to a fourth depth higher than the third depth.

Abstract translation: 描述了用于形成用于垂直TFT的双栅极结构的方法。 可以通过执行第一蚀刻工艺来形成双栅极结构，所述第一蚀刻工艺包括通过将第一组氧化物柱蚀刻到第一深度并形成第二组沟槽来形成第一组沟槽，并通过将第二组氧化物柱蚀刻到 第二深度高于第一深度，在第一组沟槽内形成第一组栅极结构，在第二组沟槽内形成第二组栅极结构，执行第二蚀刻工艺，其包括通过以下步骤形成第三组沟槽： 将第一组栅极结构从第二初始深度蚀刻到第三深度，并通过将第二组栅极结构蚀刻到高于第三深度的第四深度而形成第四组沟槽。

公开(公告)号：US08933516B1

公开(公告)日：2015-01-13

申请号：US13925662

申请日：2013-06-24

Applicant: SanDisk 3D LLC

Inventor： Ming-Che Wu ,  Wei-Te Wu ,  Yung-Tin Chen

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/788 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2454 ,  H01L27/2445 ,  H01L27/249

Abstract: A three-dimensional nonvolatile memory array includes a select layer that selectively connects vertical bit lines to horizontal bit lines. Individual select switches of the select layer include two separately controllable transistors that are connected in series between a horizontal bit line and a vertical bit line. Each transistor in a select switch is connected to a different control circuit by a different select line.

Abstract translation: 三维非易失性存储器阵列包括选择性地将垂直位线连接到水平位线的选择层。 选择层的各个选择开关包括串联连接在水平位线和垂直位线之间的两个可独立控制的晶体管。 选择开关中的每个晶体管通过不同的选择线连接到不同的控制电路。

公开(公告)号：US20160351722A1

公开(公告)日：2016-12-01

申请号：US14723038

申请日：2015-05-27

Applicant: SanDisk 3D LLC

Inventor： Guangle Zhou ,  Ming-Che Wu ,  Yung-Tin Chen

IPC: H01L29/786 ,  H01L21/265 ,  H01L29/66 ,  H01L27/24 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L21/26513 ,  H01L21/2652 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78642 ,  H01L45/16

Abstract: A multiple junction thin film transistor (TFT) is disclosed. The body of the TFT may have an n+ layer residing in a p− region of the body. The TFT may have an n+ source and an n+ drain on either side of the p− region of the body. Thus, the TFT has an n+/p−/n+/p−/n+ structure in this example. The n+ layer in the p− region increases the breakdown voltage. Also, drive current is increased. The impurity concentration in the n+ layer in the p− body and/or thickness of the n+ layer in the p− body may be tuned to increase performance of the TFT. In an alternative, the body of the TFT has a p+ layer residing in an n− region of the body. The TFT may have a p+ source and a p+ drain on either side of the p− region of the body.

Abstract translation: 公开了一种多结薄膜晶体管（TFT）。 TFT的主体可以具有驻留在身体的p-区域中的n +层。 TFT可以在身体的p-区域的任一侧上具有n +源极和n +漏极。 因此，在该示例中，TFT具有n + / p / n + / p / n +结构。 p区中的n +层增加了击穿电压。 此外，驱动电流增加。 p-体中的n +层中的杂质浓度和/或p-体中的n +层的厚度可以被调谐以提高TFT的性能。 或者，TFT的主体具有驻留在身体的n-区域中的p +层。 TFT可以在物体的p-区域的任一侧上具有p +源极和p +漏极。

公开(公告)号：US09412845B2

公开(公告)日：2016-08-09

申请号：US14519068

申请日：2014-10-20

Applicant: SANDISK 3D LLC

Inventor： Wei-Te Wu ,  Ming-Che Wu ,  Yung-Tin Chen

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/311 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51 ,  H01L27/115 ,  H01L21/8238

CPC classification number: H01L29/6675 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31111 ,  H01L21/823885 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/78648 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/141 ,  H01L45/146 ,  H01L45/16

Abstract: Methods for forming a dual gate structure for a vertical TFT are described. The dual gate structure may be formed by performing a first etching process that includes forming a first set of trenches by etching a first set of oxide pillars to a first depth and forming a second set of trenches by etching a second set of oxide pillars to a second depth higher than the first depth, forming a first set of gate structures within the first set of trenches, forming a second set of gate structures within the second set of trenches, performing a second etching process that includes forming a third set of trenches by etching the first set of gate structures from a second initial depth to a third depth and forming a fourth set of trenches by etching the second set of gate structures to a fourth depth higher than the third depth.

Abstract translation: 描述了用于形成用于垂直TFT的双栅极结构的方法。 可以通过执行第一蚀刻工艺来形成双栅极结构，所述第一蚀刻工艺包括通过将第一组氧化物柱蚀刻到第一深度并形成第二组沟槽来形成第一组沟槽，并通过将第二组氧化物柱蚀刻到 第二深度高于第一深度，在第一组沟槽内形成第一组栅极结构，在第二组沟槽内形成第二组栅极结构，执行第二蚀刻工艺，其包括通过以下步骤形成第三组沟槽： 将第一组栅极结构从第二初始深度蚀刻到第三深度，并通过将第二组栅极结构蚀刻到高于第三深度的第四深度而形成第四组沟槽。

公开(公告)号：US20140374688A1

公开(公告)日：2014-12-25

申请号：US13925662

申请日：2013-06-24

Applicant: SanDisk 3D LLC

Inventor： Ming-Che Wu ,  Wei-Te Wu ,  Yung-Tin Chen

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2454 ,  H01L27/2445 ,  H01L27/249

Abstract: A three-dimensional nonvolatile memory array includes a select layer that selectively connects vertical bit lines to horizontal bit lines. Individual select switches of the select layer include two separately controllable transistors that are connected in series between a horizontal bit line and a vertical bit line. Each transistor in a select switch is connected to a different control circuit by a different select line.

Abstract translation: 三维非易失性存储器阵列包括选择性地将垂直位线连接到水平位线的选择层。 选择层的各个选择开关包括串联连接在水平位线和垂直位线之间的两个可独立控制的晶体管。 选择开关中的每个晶体管通过不同的选择线连接到不同的控制电路。