公开(公告)号：US09653617B2

公开(公告)日：2017-05-16

申请号：US14723038

申请日：2015-05-27

Applicant: SanDisk 3D LLC

Inventor： Guangle Zhou ,  Ming-Che Wu ,  Yung-Tin Chen

IPC: H01L29/786 ,  H01L27/24 ,  H01L29/423 ,  H01L29/66 ,  H01L21/265 ,  H01L45/00

CPC classification number: H01L29/78696 ,  H01L21/26513 ,  H01L21/2652 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78642 ,  H01L45/16

Abstract: A multiple junction thin film transistor (TFT) is disclosed. The body of the TFT may have an n+ layer residing in a p− region of the body. The TFT may have an n+ source and an n+ drain on either side of the p− region of the body. Thus, the TFT has an n+/p−/n+/p−/n+ structure in this example. The n+ layer in the p− region increases the breakdown voltage. Also, drive current is increased. The impurity concentration in the n+ layer in the p− body and/or thickness of the n+ layer in the p− body may be tuned to increase performance of the TFT. In an alternative, the body of the TFT has a p+ layer residing in an n− region of the body. The TFT may have a p+ source and a p+ drain on either side of the p− region of the body.

公开(公告)号：US09583615B2

公开(公告)日：2017-02-28

申请号：US14623843

申请日：2015-02-17

Applicant: SANDISK 3D LLC

Inventor： Yung-Tin Chen ,  Guangle Zhou ,  Christopher Petti

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/739 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/11582 ,  H01L27/1203 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/78642 ,  H01L45/16

Abstract: A first patterned stack and a second patterned stack are formed over a substrate, each of which includes a bottom semiconductor layer, a bottom dielectric spacer layer, a conductive material layer, and a top dielectric spacer layer. Gate dielectrics and vertical semiconductor portions are sequentially formed on each patterned stack. Vertical semiconductor portions are removed from around the second patterned stack, while masked around the first patterned stack. Electrical dopants are introduced to top regions and bottom regions of the remaining vertical semiconductor portions to form a vertical switching device that includes the first patterned stack, while the second patterned stack functions as a horizontal interconnect structure. The vertical switching device can be a transistor or a gated diode.

Abstract translation: 第一图案化堆叠和第二图案化堆叠形成在衬底上，每个衬底包括底部半导体层，底部电介质间隔层，导电材料层和顶部电介质间隔层。 栅极电介质和垂直半导体部分依次形成在每个图案化的叠层上。 垂直半导体部分从第二图案化堆叠周围移除，同时围绕第一图案化堆叠进行掩蔽。 将电掺杂物引入剩余的垂直半导体部分的顶部区域和底部区域以形成包括第一图案化叠层的垂直开关装置，而第二图案化叠层用作水平互连结构。 垂直开关器件可以是晶体管或栅极二极管。

公开(公告)号：US20160351722A1

公开(公告)日：2016-12-01

申请号：US14723038

申请日：2015-05-27

Applicant: SanDisk 3D LLC

Inventor： Guangle Zhou ,  Ming-Che Wu ,  Yung-Tin Chen

IPC: H01L29/786 ,  H01L21/265 ,  H01L29/66 ,  H01L27/24 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L21/26513 ,  H01L21/2652 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78642 ,  H01L45/16

Abstract: A multiple junction thin film transistor (TFT) is disclosed. The body of the TFT may have an n+ layer residing in a p− region of the body. The TFT may have an n+ source and an n+ drain on either side of the p− region of the body. Thus, the TFT has an n+/p−/n+/p−/n+ structure in this example. The n+ layer in the p− region increases the breakdown voltage. Also, drive current is increased. The impurity concentration in the n+ layer in the p− body and/or thickness of the n+ layer in the p− body may be tuned to increase performance of the TFT. In an alternative, the body of the TFT has a p+ layer residing in an n− region of the body. The TFT may have a p+ source and a p+ drain on either side of the p− region of the body.

Abstract translation: 公开了一种多结薄膜晶体管（TFT）。 TFT的主体可以具有驻留在身体的p-区域中的n +层。 TFT可以在身体的p-区域的任一侧上具有n +源极和n +漏极。 因此，在该示例中，TFT具有n + / p / n + / p / n +结构。 p区中的n +层增加了击穿电压。 此外，驱动电流增加。 p-体中的n +层中的杂质浓度和/或p-体中的n +层的厚度可以被调谐以提高TFT的性能。 或者，TFT的主体具有驻留在身体的n-区域中的p +层。 TFT可以在物体的p-区域的任一侧上具有p +源极和p +漏极。

公开(公告)号：US20160240665A1

公开(公告)日：2016-08-18

申请号：US14623843

申请日：2015-02-17

Applicant: SANDISK 3D LLC

Inventor： Yung-Tin CHEN ,  Guangle Zhou ,  Christopher Petti

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/11582 ,  H01L27/1203 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/78642 ,  H01L45/16

Abstract: A first patterned stack and a second patterned stack are formed over a substrate, each of which includes a bottom semiconductor layer, a bottom dielectric spacer layer, a conductive material layer, and a top dielectric spacer layer. Gate dielectrics and vertical semiconductor portions are sequentially formed on each patterned stack. Vertical semiconductor portions are removed from around the second patterned stack, while masked around the first patterned stack. Electrical dopants are introduced to top regions and bottom regions of the remaining vertical semiconductor portions to form a vertical switching device that includes the first patterned stack, while the second patterned stack functions as a horizontal interconnect structure. The vertical switching device can be a transistor or a gated diode.

Abstract translation: 第一图案化堆叠和第二图案化堆叠形成在衬底上，每个衬底包括底部半导体层，底部电介质间隔层，导电材料层和顶部电介质间隔层。 栅极电介质和垂直半导体部分依次形成在每个图案化的叠层上。 垂直半导体部分从第二图案化堆叠周围移除，同时围绕第一图案化堆叠进行掩蔽。 将电掺杂物引入剩余垂直半导体部分的顶部区域和底部区域，以形成包括第一图案化叠层的垂直开关装置，而第二图案化叠层用作水平互连结构。 垂直开关器件可以是晶体管或栅极二极管。