公开(公告)号：US09230985B1

公开(公告)日：2016-01-05

申请号：US14515054

申请日：2014-10-15

Applicant: SanDisk 3D LLC

Inventor： Ming-Che Wu ,  Peter Rabkin ,  Tim Chen

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/786 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L29/0895 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78642

Abstract: A vertically oriented thin film transistor (TFT) having a tunnel barrier is disclosed. The tunnel barrier may be formed from a dielectric such as silicon oxide or hafnium oxide. The vertically oriented TFT selection device with tunnel barrier may serve as a selection device in a 3D memory array. The vertically oriented TFT may be used to connect/disconnect a global bit line to/from a vertical bit line in a 3D memory array. The vertically oriented TFT may be used to connect/disconnect a source line to/from a channel of a vertical NAND string in a 3D memory array. A vertical TFT with tunnel barrier has a high breakdown voltage, low leakage current, and high on current. The tunnel barrier can be at the top junction or bottom junction of the TFT.

Abstract translation: 公开了一种具有隧道势垒的垂直取向薄膜晶体管（TFT）。 隧道势垒可以由诸如氧化硅或氧化铪的电介质形成。 具有隧道势垒的垂直取向的TFT选择装置可以用作3D存储器阵列中的选择装置。 可以使用垂直取向的TFT来连接/断开与3D存储器阵列中的垂直位线的全局位线。 垂直取向的TFT可以用于将源极线连接到/离开3D存储器阵列中的垂直NAND串的通道。 具有隧道势垒的垂直TFT具有高击穿电压，低漏电流和高导通电流。 隧道势垒可以在TFT的顶部结或底部结。

公开(公告)号：US09236122B2

公开(公告)日：2016-01-12

申请号：US14340454

申请日：2014-07-24

Applicant: SANDISK 3D, LLC

Inventor： Tianhong Yan ,  George Samachisa ,  Tz-yi Liu ,  Tim Chen ,  Perumal Ratnam

IPC: G11C11/16 ,  G11C13/00 ,  H01L27/24 ,  H01L27/06 ,  H01L45/00 ,  G11C7/18 ,  H01L27/10

CPC classification number: G11C13/0069 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/003 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2207/005 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an “on” condition for the double gated vertically oriented select devices to be activated.

Abstract translation: 非易失性存储装置包括：基板; 存储单元的单片三维阵列; 连接到存储单元的字线; 全局位线 连接到存储单元的垂直位线; 和多个双门控垂直取向选择装置。 双门控垂直取向的选择装置连接到垂直位线和全局位线，使得当双门控垂直取向的选择装置被激活时，垂直位线与全局位线通信。 每个双门控垂直取向的选择装置具有两个相对于到衬底的距离彼此偏移的栅极。 双门控垂直取向选择装置的两个门都需要处于“开启”状态，双门控垂直取向的选择装置被激活。

公开(公告)号：US20150036414A1

公开(公告)日：2015-02-05

申请号：US14340454

申请日：2014-07-24

Applicant: SANDISK 3D, LLC

Inventor： Tianhong Yan ,  George Samachisa ,  Tz-yi Liu ,  Tim Chen ,  Perumal Ratnam

IPC: G11C13/00 ,  H01L27/24

CPC classification number: G11C13/0069 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/003 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2207/005 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an “on” condition for the double gated vertically oriented select devices to be activated.

Abstract translation: 非易失性存储装置包括：基板; 存储单元的单片三维阵列; 连接到存储单元的字线; 全局位线 连接到存储单元的垂直位线; 和多个双门控垂直取向选择装置。 双门控垂直取向的选择装置连接到垂直位线和全局位线，使得当双门控垂直取向的选择装置被激活时，垂直位线与全局位线通信。 每个双门控垂直取向的选择装置具有两个相对于到衬底的距离彼此偏移的栅极。 双门控垂直取向选择装置的两个门都需要处于“开启”状态，双门控垂直取向的选择装置被激活。