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公开(公告)号：US20160111517A1
公开(公告)日：2016-04-21
申请号：US14519068
申请日：2014-10-20
Applicant: SANDISK 3D LLC
Inventor： Wei-Te Wu , Ming-Che Wu , Yung-Tin Chen
IPC: H01L29/66 , H01L21/311 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L27/115 , H01L29/786 , H01L21/02
CPC classification number: H01L29/6675 , H01L21/02532 , H01L21/02595 , H01L21/31111 , H01L21/823885 , H01L27/0688 , H01L27/101 , H01L27/11526 , H01L27/11573 , H01L27/2454 , H01L27/249 , H01L29/4908 , H01L29/4916 , H01L29/4966 , H01L29/51 , H01L29/66484 , H01L29/66666 , H01L29/78648 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/1226 , H01L45/141 , H01L45/146 , H01L45/16
Abstract: Methods for forming a dual gate structure for a vertical TFT are described. The dual gate structure may be formed by performing a first etching process that includes forming a first set of trenches by etching a first set of oxide pillars to a first depth and forming a second set of trenches by etching a second set of oxide pillars to a second depth higher than the first depth, forming a first set of gate structures within the first set of trenches, forming a second set of gate structures within the second set of trenches, performing a second etching process that includes forming a third set of trenches by etching the first set of gate structures from a second initial depth to a third depth and forming a fourth set of trenches by etching the second set of gate structures to a fourth depth higher than the third depth.
Abstract translation: 描述了用于形成用于垂直TFT的双栅极结构的方法。 可以通过执行第一蚀刻工艺来形成双栅极结构，所述第一蚀刻工艺包括通过将第一组氧化物柱蚀刻到第一深度并形成第二组沟槽来形成第一组沟槽，并通过将第二组氧化物柱蚀刻到 第二深度高于第一深度，在第一组沟槽内形成第一组栅极结构，在第二组沟槽内形成第二组栅极结构，执行第二蚀刻工艺，其包括通过以下步骤形成第三组沟槽： 将第一组栅极结构从第二初始深度蚀刻到第三深度，并通过将第二组栅极结构蚀刻到高于第三深度的第四深度而形成第四组沟槽。
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公开(公告)号：US08933516B1
公开(公告)日：2015-01-13
申请号：US13925662
申请日：2013-06-24
Applicant: SanDisk 3D LLC
Inventor： Ming-Che Wu , Wei-Te Wu , Yung-Tin Chen
IPC: H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/788 , H01L27/24 , H01L45/00
CPC classification number: H01L27/2454 , H01L27/2445 , H01L27/249
Abstract: A three-dimensional nonvolatile memory array includes a select layer that selectively connects vertical bit lines to horizontal bit lines. Individual select switches of the select layer include two separately controllable transistors that are connected in series between a horizontal bit line and a vertical bit line. Each transistor in a select switch is connected to a different control circuit by a different select line.
Abstract translation: 三维非易失性存储器阵列包括选择性地将垂直位线连接到水平位线的选择层。 选择层的各个选择开关包括串联连接在水平位线和垂直位线之间的两个可独立控制的晶体管。 选择开关中的每个晶体管通过不同的选择线连接到不同的控制电路。
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公开(公告)号：US09412845B2
公开(公告)日：2016-08-09
申请号：US14519068
申请日：2014-10-20
Applicant: SANDISK 3D LLC
Inventor： Wei-Te Wu , Ming-Che Wu , Yung-Tin Chen
IPC: H01L29/66 , H01L29/786 , H01L21/311 , H01L21/02 , H01L29/49 , H01L29/51 , H01L27/115 , H01L21/8238
CPC classification number: H01L29/6675 , H01L21/02532 , H01L21/02595 , H01L21/31111 , H01L21/823885 , H01L27/0688 , H01L27/101 , H01L27/11526 , H01L27/11573 , H01L27/2454 , H01L27/249 , H01L29/4908 , H01L29/4916 , H01L29/4966 , H01L29/51 , H01L29/66484 , H01L29/66666 , H01L29/78648 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/1226 , H01L45/141 , H01L45/146 , H01L45/16
Abstract: Methods for forming a dual gate structure for a vertical TFT are described. The dual gate structure may be formed by performing a first etching process that includes forming a first set of trenches by etching a first set of oxide pillars to a first depth and forming a second set of trenches by etching a second set of oxide pillars to a second depth higher than the first depth, forming a first set of gate structures within the first set of trenches, forming a second set of gate structures within the second set of trenches, performing a second etching process that includes forming a third set of trenches by etching the first set of gate structures from a second initial depth to a third depth and forming a fourth set of trenches by etching the second set of gate structures to a fourth depth higher than the third depth.
Abstract translation: 描述了用于形成用于垂直TFT的双栅极结构的方法。 可以通过执行第一蚀刻工艺来形成双栅极结构，所述第一蚀刻工艺包括通过将第一组氧化物柱蚀刻到第一深度并形成第二组沟槽来形成第一组沟槽，并通过将第二组氧化物柱蚀刻到 第二深度高于第一深度，在第一组沟槽内形成第一组栅极结构，在第二组沟槽内形成第二组栅极结构，执行第二蚀刻工艺，其包括通过以下步骤形成第三组沟槽： 将第一组栅极结构从第二初始深度蚀刻到第三深度，并通过将第二组栅极结构蚀刻到高于第三深度的第四深度而形成第四组沟槽。
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公开(公告)号：US20140374688A1
公开(公告)日：2014-12-25
申请号：US13925662
申请日：2013-06-24
Applicant: SanDisk 3D LLC
Inventor： Ming-Che Wu , Wei-Te Wu , Yung-Tin Chen
CPC classification number: H01L27/2454 , H01L27/2445 , H01L27/249
Abstract: A three-dimensional nonvolatile memory array includes a select layer that selectively connects vertical bit lines to horizontal bit lines. Individual select switches of the select layer include two separately controllable transistors that are connected in series between a horizontal bit line and a vertical bit line. Each transistor in a select switch is connected to a different control circuit by a different select line.
Abstract translation: 三维非易失性存储器阵列包括选择性地将垂直位线连接到水平位线的选择层。 选择层的各个选择开关包括串联连接在水平位线和垂直位线之间的两个可独立控制的晶体管。 选择开关中的每个晶体管通过不同的选择线连接到不同的控制电路。
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