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    MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME
    2.
    发明申请
    MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME 有权
    具有与转向元件共享材料层的存储元件的存储单元及其形成方法

    公开(公告)号：US20130175492A1

    公开(公告)日：2013-07-11

    申请号：US13783585

    申请日：2013-03-04

    Applicant: SanDisk 3D LLC

    Inventor： Yung-Tin Chen ,  Chuanbin Pan ,  Andrei Mihnea ,  Steven Maxwell ,  Kun Hou

    IPC: H01L45/00

    CPC classification number: H01L45/146 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1616 ,  Y10S438/957

    Abstract: In some embodiments, a memory cell is provided that includes a metal-insulator-metal stack and a steering element coupled to the metal-insulator-metal stack. The metal-insulator-metal stack includes a first conductive layer, a reversible resistivity switching layer above the first conductive layer, and a second conductive layer above the reversible resistivity switching layer. The first conductive layer and/or the second conductive layer includes a first semiconductor material layer. The steering element includes the first semiconductor material layer. Numerous other aspects are provided.

    Abstract translation: 在一些实施例中，提供了包括金属 - 绝缘体 - 金属堆叠和耦合到金属 - 绝缘体 - 金属堆叠的操纵元件的存储单元。 金属 - 绝缘体 - 金属堆叠包括第一导电层，第一导电层上方的可逆电阻率开关层和可逆电阻率切换层上方的第二导电层。 第一导电层和/或第二导电层包括第一半导体材料层。 该转向元件包括第一半导体材料层。 提供了许多其他方面。

    MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME
    5.
    发明申请
    MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME 有权
    具有与转向元件共享材料层的存储元件的存储单元及其形成方法

    公开(公告)号：US20140284538A1

    公开(公告)日：2014-09-25

    申请号：US14299240

    申请日：2014-06-09

    Applicant: SANDISK 3D LLC

    Inventor： Yung-Tin Chen ,  Chuanbin Pan ,  Andrei Mihnea ,  Steven Maxwell ,  Kun Hou

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/146 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1616 ,  Y10S438/957

    Abstract: A memory cell is provided that includes a steering element, a metal-insulator-metal stack coupled in series with the steering element, and a conductor above the metal-insulator-metal stack. The steering element includes a diode having an n-region and a p-region. The metal-insulator-metal stack includes a reversible resistivity-switching material between a top electrode and a bottom electrode, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer disposed between the metal-insulator-metal stack and the conductor. The bottom electrode includes the n-region or the p-region of the diode, and the reversible resistivity-switching material is directly adjacent the n-region or the p-region of the diode. Numerous other aspects are provided.

    Abstract translation: 提供了一种存储单元，其包括转向元件，与转向元件串联耦合的金属 - 绝缘体 - 金属叠层以及金属 - 绝缘体 - 金属叠层上方的导体。 该转向元件包括具有n区和p区的二极管。 金属 - 绝缘体 - 金属堆叠包括在顶部电极和底部电极之间的可逆电阻率切换材料，并且顶部电极包括高度掺杂的半导体材料。 存储单元不包括设置在金属 - 绝缘体 - 金属叠层和导体之间的金属层。 底部电极包括二极管的n区域或p区域，并且可逆电阻率切换材料直接邻近二极管的n区域或p区域。 提供了许多其他方面。

    LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE
    6.
    发明申请
    LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE 有权
    低成型电压非易失存储器件

    公开(公告)号：US20130170283A1

    公开(公告)日：2013-07-04

    申请号：US13709349

    申请日：2012-12-10

    Applicant: Sandisk 3D LLC

    Inventor： Zhida Lan ,  Roy E. Scheuerlein ,  Tong Zhang ,  Kun Hou ,  Perumal Ratnam

    IPC: G11C13/00

    CPC classification number: G11C13/0097 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

    Abstract: A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are provided across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that the bit line acts as a cathode and the word line acts as an anode, with the cathode having a lower electron injection energy barrier to the switching material than the anode.

    Abstract translation: 存储元件的三维阵列，其响应于在其上施加的电压差而可逆地改变电导水平。 存储元件设置在跨越半导体衬底的不同距离上的多个平面中。 所有平面的存储元件所连接的位线从衬底垂直定向并穿过多个平面。 存储器元件可以被设置为低电阻状态，并且在标准操作期间通过偏置字线和位线上的适当电压而复位到高电阻状态。 在标准操作之前，存储元件进行成形操作，在此期间，通过位线的电流受到限制。 在具有极性的成形期间，将形成电压施加到存储元件，使得位线用作阴极，并且字线用作阳极，阴极与开关材料相比具有较低的电子注入能量势垒。

    Memory cells having storage elements that share material layers with steering elements and methods of forming the same
    8.
    发明授权
    Memory cells having storage elements that share material layers with steering elements and methods of forming the same 有权
    具有与转向元件共享材料层的存储元件的存储单元及其形成方法

    公开(公告)号：US08969845B2

    公开(公告)日：2015-03-03

    申请号：US14299240

    申请日：2014-06-09

    Applicant: SanDisk 3D LLC

    Inventor： Yung-Tin Chen ,  Chuanbin Pan ,  Andrei Mihnea ,  Steven Maxwell ,  Kun Hou

    IPC: H01L47/00 ,  H01L29/02 ,  H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/146 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1616 ,  Y10S438/957

    Abstract: A memory cell is provided that includes a steering element, a metal-insulator-metal stack coupled in series with the steering element, and a conductor above the metal-insulator-metal stack. The steering element includes a diode having an n-region and a p-region. The metal-insulator-metal stack includes a reversible resistivity-switching material between a top electrode and a bottom electrode, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer disposed between the metal-insulator-metal stack and the conductor. The bottom electrode includes the n-region or the p-region of the diode, and the reversible resistivity-switching material is directly adjacent the n-region or the p-region of the diode. Numerous other aspects are provided.

    Abstract translation: 提供了一种存储单元，其包括转向元件，与转向元件串联耦合的金属 - 绝缘体 - 金属叠层以及金属 - 绝缘体 - 金属叠层上方的导体。 该转向元件包括具有n区和p区的二极管。 金属 - 绝缘体 - 金属堆叠包括在顶部电极和底部电极之间的可逆电阻率切换材料，并且顶部电极包括高度掺杂的半导体材料。 存储单元不包括设置在金属 - 绝缘体 - 金属叠层和导体之间的金属层。 底部电极包括二极管的n区域或p区域，并且可逆电阻率切换材料直接邻近二极管的n区域或p区域。 提供了许多其他方面。

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