公开(公告)号：US20160020389A1

公开(公告)日：2016-01-21

申请号：US14716382

申请日：2015-05-19

Applicant: SANDISK 3D LLC

Inventor： Perumal Ratnam ,  Christopher Petti ,  Tianhong Yan

IPC: H01L45/00

CPC classification number: G11C13/004 ,  G06F11/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1204 ,  G11C2213/71 ,  G11C2216/10 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/786 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/146

Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

Abstract translation: 描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。 在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。 可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻 其不直接连接到本征多晶硅部分。 本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

公开(公告)号：US09576660B2

公开(公告)日：2017-02-21

申请号：US14996144

申请日：2016-01-14

Applicant: SANDISK 3D LLC

Inventor： Zhida Lan ,  Roy E. Scheuerlein ,  Tong Zhang ,  Kun Hou ,  Perumal Ratnam

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0097 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

Abstract: A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.

Abstract translation: 存储元件的三维阵列，其响应于在其上施加的电压差而可逆地改变电导水平。 存储器元件可以被设置为低电阻状态，并且在标准操作期间通过偏置字线和位线上的适当电压而复位到高电阻状态。 在标准操作之前，存储元件进行成形操作，在此期间，通过位线的电流被限制。 在成形期间，将形成电压施加到存储元件，其极性使得较高的电压被施加到阳极，而较低的电压施加到阴极。

公开(公告)号：US09484093B2

公开(公告)日：2016-11-01

申请号：US14715583

申请日：2015-05-18

Applicant: SANDISK 3D LLC

Inventor： Perumal Ratnam ,  Christopher Petti ,  Tianhong Yan

IPC: G11C11/00 ,  G11C13/00 ,  G06F11/10 ,  H01L27/24 ,  H01L29/786 ,  H01L45/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C7/12 ,  G11C7/18 ,  G11C29/02 ,  G11C29/12

CPC classification number: G11C13/004 ,  G06F11/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1204 ,  G11C2213/71 ,  G11C2216/10 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/786 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/146

Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

Abstract translation: 描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。 在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。 可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻 其不直接连接到本征多晶硅部分。 本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

公开(公告)号：US09484092B2

公开(公告)日：2016-11-01

申请号：US14715562

申请日：2015-05-18

Applicant: SANDISK 3D LLC

Inventor： Perumal Ratnam

IPC: G11C13/00 ,  G06F11/10 ,  H01L27/24 ,  H01L29/786 ,  H01L45/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C7/12 ,  G11C7/18 ,  G11C29/02 ,  G11C29/12

CPC classification number: G11C13/004 ,  G06F11/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1204 ,  G11C2213/71 ,  G11C2216/10 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/786 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/146

Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

Abstract translation: 描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。 在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。 可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻 其不直接连接到本征多晶硅部分。 本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

公开(公告)号：US20160019960A1

公开(公告)日：2016-01-21

申请号：US14715575

申请日：2015-05-18

Applicant: SANDISK 3D LLC

Inventor： Perumal Ratnam ,  Christopher Petti ,  Tianhong Yan

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G06F11/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1204 ,  G11C2213/71 ,  G11C2216/10 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/786 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/146

Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

Abstract translation: 描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。 在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。 可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻 其不直接连接到本征多晶硅部分。 本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

公开(公告)号：US20160019953A1

公开(公告)日：2016-01-21

申请号：US14715579

申请日：2015-05-18

Applicant: SANDISK 3D LLC

Inventor： Perumal Ratnam ,  Christopher Petti ,  Tianhong Yan

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G06F11/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1204 ,  G11C2213/71 ,  G11C2216/10 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/786 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/146

Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

Abstract translation: 描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。 在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。 可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻 其不直接连接到本征多晶硅部分。 本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

公开(公告)号：US09455301B2

公开(公告)日：2016-09-27

申请号：US14715579

申请日：2015-05-18

Applicant: SANDISK 3D LLC

Inventor： Perumal Ratnam ,  Christopher Petti ,  Tianhong Yan

IPC: H01L27/24 ,  G11C13/00 ,  G06F11/10 ,  H01L29/786 ,  H01L45/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C7/12 ,  G11C7/18 ,  G11C29/02 ,  G11C29/12

CPC classification number: G11C13/004 ,  G06F11/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1204 ,  G11C2213/71 ,  G11C2216/10 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/786 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/146

Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

Abstract translation: 在存储器操作期间通过存储器阵列的未选择存储单元减少漏电流的方法。 在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。 可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻 其不直接连接到本征多晶硅部分。 本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

公开(公告)号：US20160019957A1

公开(公告)日：2016-01-21

申请号：US14715586

申请日：2015-05-18

Applicant: SANDISK 3D LLC

Inventor： Perumal Ratnam ,  Christopher Petti ,  Tianhong Yan

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G06F11/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1204 ,  G11C2213/71 ,  G11C2216/10 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/786 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/146

Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

Abstract translation: 描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。 在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。 可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻 其不直接连接到本征多晶硅部分。 本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

公开(公告)号：US20160019952A1

公开(公告)日：2016-01-21

申请号：US14715562

申请日：2015-05-18

Applicant: SANDISK 3D LLC

Inventor： Perumal Ratnam

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G06F11/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1204 ,  G11C2213/71 ,  G11C2216/10 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/786 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/146

Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

Abstract translation: 描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。 在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。 可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻 其不直接连接到本征多晶硅部分。 本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

公开(公告)号：US20130170283A1

公开(公告)日：2013-07-04

申请号：US13709349

申请日：2012-12-10

Applicant: Sandisk 3D LLC

Inventor： Zhida Lan ,  Roy E. Scheuerlein ,  Tong Zhang ,  Kun Hou ,  Perumal Ratnam

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

Abstract: A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are provided across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that the bit line acts as a cathode and the word line acts as an anode, with the cathode having a lower electron injection energy barrier to the switching material than the anode.

Abstract translation: 存储元件的三维阵列，其响应于在其上施加的电压差而可逆地改变电导水平。 存储元件设置在跨越半导体衬底的不同距离上的多个平面中。 所有平面的存储元件所连接的位线从衬底垂直定向并穿过多个平面。 存储器元件可以被设置为低电阻状态，并且在标准操作期间通过偏置字线和位线上的适当电压而复位到高电阻状态。 在标准操作之前，存储元件进行成形操作，在此期间，通过位线的电流受到限制。 在具有极性的成形期间，将形成电压施加到存储元件，使得位线用作阴极，并且字线用作阳极，阴极与开关材料相比具有较低的电子注入能量势垒。