-
1.发明授权Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same 有权具有使用双极存储元件的存储器单元的多级存储器阵列及其形成方法公开(公告)号：US09105576B2
公开(公告)日：2015-08-11
申请号：US14456158
申请日：2014-08-11
Applicant: SanDisk 3D LLC
Inventor： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
CPC classification number: H01L27/2481 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1608
Abstract: In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.
Abstract translation: 在一些实施例中，提供了一种存储器阵列，其包括（1）具有（a）第一导电线的第一存储器单元; （b）形成在第一导线之上的第一双极存储元件; 和（c）形成在所述第一双极存储元件上方的第二导线; 以及（2）形成在所述第一存储单元上方的第二存储单元，并且具有（a）形成在所述第二导线上方的第二双极存储元件; 和（b）形成在第二双极存储元件上方的第三导线。 第一和第二存储单元共享第二导线; 第一双极存储元件在第一存储单元内具有第一存储元件极性取向; 所述第二双极存储元件在所述第二存储单元内具有第二存储元件极性取向; 并且第二存储元件极性取向与第一存储元件极性取向相反。 提供了许多其他方面。
-
Patent Agency Ranking
2.发明授权Memory cells having storage elements that share material layers with steering elements and methods of forming the same 有权具有与转向元件共享材料层的存储元件的存储单元及其形成方法公开(公告)号：US08981331B2
公开(公告)日：2015-03-17
申请号：US13783585
申请日：2013-03-04
Applicant: SanDisk 3D LLC
Inventor： Yung-Tin Chen , Chuanbin Pan , Andrei Mihnea , Steven Maxwell , Kun Hou
IPC: H01L47/00 , H01L21/8238 , H01L45/00 , H01L27/24
CPC classification number: H01L45/146 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1616 , Y10S438/957
Abstract: In some embodiments, a memory cell is provided that includes a metal-insulator-metal stack and a steering element coupled to the metal-insulator-metal stack. The metal-insulator-metal stack includes a first conductive layer, a reversible resistivity switching layer above the first conductive layer, and a second conductive layer above the reversible resistivity switching layer. The first conductive layer and/or the second conductive layer includes a first semiconductor material layer. The steering element includes the first semiconductor material layer. Numerous other aspects are provided.
Abstract translation: 在一些实施例中，提供了包括金属 - 绝缘体 - 金属堆叠和耦合到金属 - 绝缘体 - 金属堆叠的操纵元件的存储单元。 金属 - 绝缘体 - 金属堆叠包括第一导电层，第一导电层上方的可逆电阻率开关层和可逆电阻率切换层上方的第二导电层。 第一导电层和/或第二导电层包括第一半导体材料层。 该转向元件包括第一半导体材料层。 提供了许多其他方面。
-
3.发明申请MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME 有权具有与转向元件共享材料层的存储元件的存储单元及其形成方法公开(公告)号：US20130175492A1
公开(公告)日：2013-07-11
申请号：US13783585
申请日：2013-03-04
Applicant: SanDisk 3D LLC
Inventor： Yung-Tin Chen , Chuanbin Pan , Andrei Mihnea , Steven Maxwell , Kun Hou
IPC: H01L45/00
CPC classification number: H01L45/146 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1616 , Y10S438/957
Abstract: In some embodiments, a memory cell is provided that includes a metal-insulator-metal stack and a steering element coupled to the metal-insulator-metal stack. The metal-insulator-metal stack includes a first conductive layer, a reversible resistivity switching layer above the first conductive layer, and a second conductive layer above the reversible resistivity switching layer. The first conductive layer and/or the second conductive layer includes a first semiconductor material layer. The steering element includes the first semiconductor material layer. Numerous other aspects are provided.
Abstract translation: 在一些实施例中，提供了包括金属 - 绝缘体 - 金属堆叠和耦合到金属 - 绝缘体 - 金属堆叠的操纵元件的存储单元。 金属 - 绝缘体 - 金属堆叠包括第一导电层，第一导电层上方的可逆电阻率开关层和可逆电阻率切换层上方的第二导电层。 第一导电层和/或第二导电层包括第一半导体材料层。 该转向元件包括第一半导体材料层。 提供了许多其他方面。
-
4.发明申请MEMORY CELLS HAVING STORAGE ELEMENTS THAT SHARE MATERIAL LAYERS WITH STEERING ELEMENTS AND METHODS OF FORMING THE SAME 有权具有与转向元件共享材料层的存储元件的存储单元及其形成方法公开(公告)号：US20140284538A1
公开(公告)日：2014-09-25
申请号：US14299240
申请日：2014-06-09
Applicant: SANDISK 3D LLC
Inventor： Yung-Tin Chen , Chuanbin Pan , Andrei Mihnea , Steven Maxwell , Kun Hou
CPC classification number: H01L45/146 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1616 , Y10S438/957
Abstract: A memory cell is provided that includes a steering element, a metal-insulator-metal stack coupled in series with the steering element, and a conductor above the metal-insulator-metal stack. The steering element includes a diode having an n-region and a p-region. The metal-insulator-metal stack includes a reversible resistivity-switching material between a top electrode and a bottom electrode, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer disposed between the metal-insulator-metal stack and the conductor. The bottom electrode includes the n-region or the p-region of the diode, and the reversible resistivity-switching material is directly adjacent the n-region or the p-region of the diode. Numerous other aspects are provided.
Abstract translation: 提供了一种存储单元，其包括转向元件，与转向元件串联耦合的金属 - 绝缘体 - 金属叠层以及金属 - 绝缘体 - 金属叠层上方的导体。 该转向元件包括具有n区和p区的二极管。 金属 - 绝缘体 - 金属堆叠包括在顶部电极和底部电极之间的可逆电阻率切换材料，并且顶部电极包括高度掺杂的半导体材料。 存储单元不包括设置在金属 - 绝缘体 - 金属叠层和导体之间的金属层。 底部电极包括二极管的n区域或p区域，并且可逆电阻率切换材料直接邻近二极管的n区域或p区域。 提供了许多其他方面。
-
5.发明授权Memory cells having storage elements that share material layers with steering elements and methods of forming the same 有权具有与转向元件共享材料层的存储元件的存储单元及其形成方法公开(公告)号：US08969845B2
公开(公告)日：2015-03-03
申请号：US14299240
申请日：2014-06-09
Applicant: SanDisk 3D LLC
Inventor： Yung-Tin Chen , Chuanbin Pan , Andrei Mihnea , Steven Maxwell , Kun Hou
CPC classification number: H01L45/146 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1616 , Y10S438/957
Abstract: A memory cell is provided that includes a steering element, a metal-insulator-metal stack coupled in series with the steering element, and a conductor above the metal-insulator-metal stack. The steering element includes a diode having an n-region and a p-region. The metal-insulator-metal stack includes a reversible resistivity-switching material between a top electrode and a bottom electrode, and the top electrode includes a highly doped semiconductor material. The memory cell does not include a metal layer disposed between the metal-insulator-metal stack and the conductor. The bottom electrode includes the n-region or the p-region of the diode, and the reversible resistivity-switching material is directly adjacent the n-region or the p-region of the diode. Numerous other aspects are provided.
Abstract translation: 提供了一种存储单元，其包括转向元件，与转向元件串联耦合的金属 - 绝缘体 - 金属叠层以及金属 - 绝缘体 - 金属叠层上方的导体。 该转向元件包括具有n区和p区的二极管。 金属 - 绝缘体 - 金属堆叠包括在顶部电极和底部电极之间的可逆电阻率切换材料，并且顶部电极包括高度掺杂的半导体材料。 存储单元不包括设置在金属 - 绝缘体 - 金属叠层和导体之间的金属层。 底部电极包括二极管的n区域或p区域，并且可逆电阻率切换材料直接邻近二极管的n区域或p区域。 提供了许多其他方面。
-
6.发明申请MULTI-LEVEL MEMORY ARRAYS WITH MEMORY CELLS THAT EMPLOY BIPOLAR STORAGE ELEMENTS AND METHODS OF FORMING THE SAME 有权具有使用双极存储元件的存储器单元的多级存储器阵列及其形成方法公开(公告)号：US20140346433A1
公开(公告)日：2014-11-27
申请号：US14456158
申请日：2014-08-11
Applicant: SanDisk 3D LLC
Inventor： Yung-Tin Chen , Andrei Mihnea , Roy E. Scheuerlein , Luca Fasoli
CPC classification number: H01L27/2481 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1608
Abstract: In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.
Abstract translation: 在一些实施例中，提供了一种存储器阵列，其包括（1）具有（a）第一导电线的第一存储器单元; （b）形成在第一导线之上的第一双极存储元件; 和（c）形成在所述第一双极存储元件上方的第二导线; 以及（2）形成在所述第一存储单元上方的第二存储单元，并且具有（a）形成在所述第二导线上方的第二双极存储元件; 和（b）形成在第二双极存储元件上方的第三导线。 第一和第二存储单元共享第二导线; 第一双极存储元件在第一存储单元内具有第一存储元件极性取向; 所述第二双极存储元件在所述第二存储单元内具有第二存储元件极性取向; 并且第二存储元件极性取向与第一存储元件极性取向相反。 提供了许多其他方面。
-
-
-
-
-
Search Results
6
records
(took 0.038 seconds)
