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    Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same
    1.
    发明授权
    Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same 有权
    具有使用双极存储元件的存储器单元的多级存储器阵列及其形成方法

    公开(公告)号：US09105576B2

    公开(公告)日：2015-08-11

    申请号：US14456158

    申请日：2014-08-11

    Applicant: SanDisk 3D LLC

    Inventor： Yung-Tin Chen ,  Andrei Mihnea ,  Roy E. Scheuerlein ,  Luca Fasoli

    IPC: H01L47/00 ,  H01L27/24 ,  G11C11/56 ,  G11C13/00 ,  H01L45/00

    CPC classification number: H01L27/2481 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/55 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

    Abstract: In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.

    Abstract translation: 在一些实施例中，提供了一种存储器阵列，其包括（1）具有（a）第一导电线的第一存储器单元; （b）形成在第一导线之上的第一双极存储元件; 和（c）形成在所述第一双极存储元件上方的第二导线; 以及（2）形成在所述第一存储单元上方的第二存储单元，并且具有（a）形成在所述第二导线上方的第二双极存储元件; 和（b）形成在第二双极存储元件上方的第三导线。 第一和第二存储单元共享第二导线; 第一双极存储元件在第一存储单元内具有第一存储元件极性取向; 所述第二双极存储元件在所述第二存储单元内具有第二存储元件极性取向; 并且第二存储元件极性取向与第一存储元件极性取向相反。 提供了许多其他方面。

    3D MEMORY WITH VERTICAL BIT LINES AND STAIRCASE WORD LINES AND VERTICAL SWITCHES AND METHODS THEREOF
    4.
    发明申请
    3D MEMORY WITH VERTICAL BIT LINES AND STAIRCASE WORD LINES AND VERTICAL SWITCHES AND METHODS THEREOF 有权
    具有垂直位线和立柱字线和垂直开关的3D存储器及其方法

    公开(公告)号：US20130339571A1

    公开(公告)日：2013-12-19

    申请号：US13835032

    申请日：2013-03-15

    Applicant: SANDISK 3D LLC

    Inventor： Raul Adrian Cernea ,  Roy E. Scheuerlein

    IPC: G06F12/02

    CPC classification number: H01L27/249 ,  G06F12/0238 ,  G11C5/025 ,  G11C5/06 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/71 ,  H01L21/76877 ,  H01L27/1052 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

    Abstract: A 3D memory with vertical local bit lines global bit lines has an in-line vertical switch in the form of a thin film transistor (TFT) formed as a vertical structure, to switch a local bit line to a global bit line. The TFT is implemented to switch a maximum of current carried by the local bit line by a strongly coupled select gate which must be fitted within the space around the local bit line. Maximum thickness of the select gate is implemented with the select gate exclusively occupying the space along the x-direction from both sides of the local bit line. The switches for odd and even bit lines of the row are staggered and offset in the z-direction so that the select gates of even and odd local bit lines are not coincident along the x-direction. The switching is further enhanced with a wrap-around select gate.

    Abstract translation: 具有垂直局部位线的3D存储器全局位线具有形成为垂直结构的薄膜晶体管（TFT）形式的在线垂直开关，以将局部位线切换到全局位线。 TFT被实现为通过强耦合的选择栅极来切换局部位线所承载的最大电流，该选择栅极必须装配在局部位线周围的空间内。 选择栅极的最大厚度是通过选择栅极实现的，该选择栅极从局部位线的两侧专门占据x方向的空间。 该行的奇数和偶数位线的开关在z方向上交错和偏移，使得偶数和奇数局部位线的选择栅极沿x方向不重合。 通过环绕选择门进一步增强切换。

    Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines
    5.
    发明授权
    Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines 有权
    具有垂直位线上方和下方交错垂直选择器件的三维非易失性存储器

    公开(公告)号：US09171584B2

    公开(公告)日：2015-10-27

    申请号：US13886874

    申请日：2013-05-03

    Applicant: SANDISK 3D LLC

    Inventor： Roy E. Scheuerlein ,  Chang Siau

    IPC: G11C11/00 ,  G11C5/06 ,  G11C13/00 ,  H01L27/24 ,  G11C7/18 ,  H01L45/00

    CPC classification number: G11C5/06 ,  G11C5/063 ,  G11C7/18 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/71 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146

    Abstract: A three-dimensional array of memory elements reversibly change a level of electrical conductance/resistance in response to one or more voltage differences being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Local bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. Vertically oriented select devices are used to connect the local bit lines to global bit lines. A first subset of the vertically oriented select devices are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices (interleaved with the first subset of the vertically oriented select devices) are positioned below the vertically oriented bit lines.

    Abstract translation: 存储元件的三维阵列响应于在其上施加的一个或多个电压差而可逆地改变电导/电阻的水平。 存储元件跨越位于半导体衬底上方不同距离的多个平面形成。 所有平面的存储元件连接到的局部位线从衬底垂直定向并穿过多个平面。 垂直定向选择器件用于将局部位线连接到全局位线。 垂直取向的选择装置的第一子集位于垂直取向的位线上方，垂直取向的选择装置的第二子集（与垂直取向的选择装置的第一子集交错）位于垂直取向的位线下方。

    Method of operating FET low current 3D Re-RAM
    6.
    发明授权
    Method of operating FET low current 3D Re-RAM 有权
    操作FET低电流3D Re-RAM的方法

    公开(公告)号：US08995169B1

    公开(公告)日：2015-03-31

    申请号：US14025442

    申请日：2013-09-12

    Applicant: SanDisk 3D LLC

    Inventor： Abhijit Bandyopadhyay ,  Roy E. Scheuerlein ,  Chandrasekhar R. Gorla ,  Brian Le

    IPC: G11C13/00 ,  G11C11/56 ,  G11C7/00

    CPC classification number: G11C13/0069 ,  G11C7/00 ,  G11C11/5614 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C16/3454 ,  G11C2013/0083 ,  G11C2213/71 ,  G11C2213/78 ,  G11C2213/79

    Abstract: Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.

    Abstract translation: 本文公开了操作ReRAM存储器。 可以在最初对它们进行编程之前训练存储器单元。 训练可能有助于建立渗透路径。 在某些方面，当训练和编程时，晶体管限制存储器单元的电流。 在训练期间使用更高的电流限制，这调节存储器单元以进行更好的编程。 非存储器可以在单极模式下操作。 存储器单元可以存储每个存储器单元的多个位。 可以将存储器单元从其当前状态直接设置为一个至少两个数据状态。 存储单元可以直接复位到具有下一个最高电阻的状态。 诸如脉冲宽度和/或幅度的程序条件可以取决于存储器单元被设置到的状态。 较高的能量可用于编程更高的电流状态。

    METHODS AND APPARATUS FOR REDUCING PROGRAMMING TIME OF A MEMORY CELL
    10.
    发明申请
    METHODS AND APPARATUS FOR REDUCING PROGRAMMING TIME OF A MEMORY CELL 有权
    降低记忆体编程时间的方法和装置

    公开(公告)号：US20140269129A1

    公开(公告)日：2014-09-18

    申请号：US14290888

    申请日：2014-05-29

    Applicant: SanDisk 3D LLC

    Inventor： Tyler J. Thorp ,  Roy E. Scheuerlein

    IPC: G11C7/12 ,  G11C8/08 ,  G11C7/06

    CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0061 ,  G11C13/0069

    Abstract: A method is provided for programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line. During a first predetermined time interval, the word line is switched from a first standby voltage to a first voltage, the bit line is switched from a second standby voltage to a predetermined voltage, and a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell. During a second predetermined time interval, the word line is switched from the first voltage to a second voltage, and a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell. Numerous other aspects are provided.

    Abstract translation: 提供了一种用于对具有耦合到字线的第一端子和耦合到位线的第二端子的存储单元进行编程的方法。 在第一预定时间间隔期间，字线从第一备用电压切换到第一电压，位线从第二待机电压切换到预定电压，并且跨第一和第二端子的电压降是安全的 不对存储单元进行编程的电压。 在第二预定时间间隔期间，字线从第一电压切换到第二电压，并且跨越第一和第二端子的电压降是足以编程存储器单元的编程电压。 提供了许多其他方面。

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