公开(公告)号：US08039874B2

公开(公告)日：2011-10-18

申请号：US11902391

申请日：2007-09-21

Applicant: Masatomo Eimitsu ,  Takanori Saeki

Inventor： Masatomo Eimitsu ,  Takanori Saeki

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  Y10S257/909 ,  Y10S257/919

Abstract: According to an aspect of the present invention, there is provided a semiconductor IC that includes a plurality of standard cells arranged in a first direction on a semiconductor substrate, and a first diffusion layer connected to a first power source and a second diffusion layer connected to a second power source in the each standard cell, wherein the first diffusion layers as well as the second diffusion layers of neighboring standard cells are integrally formed.

Abstract translation: 根据本发明的一个方面，提供了一种半导体IC，其包括在半导体衬底上沿第一方向布置的多个标准单元，以及连接到第一电源的第一扩散层和连接到 在每个标准单元中的第二电源，其中相邻标准单元的第一扩散层以及第二扩散层是一体形成的。

公开(公告)号：US20110241121A1

公开(公告)日：2011-10-06

申请号：US13009602

申请日：2011-01-19

Applicant: OhKyum Kwon ,  Byungsun Kim ,  Taejung Lee

Inventor： OhKyum Kwon ,  Byungsun Kim ,  Taejung Lee

IPC: H01L27/11

CPC classification number: H01L27/1104 ,  H01L27/0207 ,  H01L27/11 ,  Y10S257/909

Abstract: An SRAM cell of a semiconductor device includes a load transistor, a driver transistor and an access transistor. First source/drains of the load, driver and access transistors are connected to a node. A power line, a ground line and a bit line are electrically connected to second source/drains of the load transistor, the driver transistor and the access transistor. The power line, the ground line and the bit line are disposed at substantially the same level to extend in a first direction. A word line is electrically connected to a gate of the access transistor to extend in a second direction perpendicular to the first direction. The word line is disposed at a different level from the level of the power line, the ground line and the bit line.

Abstract translation: 半导体器件的SRAM单元包括负载晶体管，驱动晶体管和存取晶体管。 负载，驱动器和存取晶体管的第一源/漏极连接到节点。 电力线，地线和位线电连接到负载晶体管，驱动晶体管和存取晶体管的第二源极/漏极。 电力线，地线和位线被设置在基本上相同的水平面上，以沿第一方向延伸。 字线电连接到存取晶体管的栅极，以在垂直于第一方向的第二方向延伸。 字线设置在与电力线，地线和位线的电平不同的水平上。

公开(公告)号：US07651905B2

公开(公告)日：2010-01-26

申请号：US11110457

申请日：2005-04-19

Applicant: Ashok Kumar Kapoor

Inventor： Ashok Kumar Kapoor

IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/10 ,  H01L29/739 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/11 ,  G11C11/412 ,  H01L21/28052 ,  H01L29/4916 ,  H01L29/665 ,  Y10S257/903 ,  Y10S257/905 ,  Y10S257/909

Abstract: An apparatus and method for the reduction of gate leakage in deep sub-micron metal oxide semiconductor (MOS) transistors, especially useful for those used in a cross coupled static random access memory (SRAM) cell, is disclosed. In accordance with the invention, the active element of the SRAM cell is used to reduce the voltage on the gate of its transistor without impacting the switching speed of the circuit. Because the load on the output of the inverter is fixed, a reduction in the gate current is optimized to minimize the impact on the switching waveform of the memory cell. An active element formed by two materials with different Fermi potentials is used as a rectifying junction or diode. The rectifying junction also has a large parallel leakage path, which allows a finite current flow when a signal of opposite polarity is applied across this device.

Abstract translation: 公开了一种用于减少深亚微米金属氧化物半导体（MOS）晶体管中的栅极泄漏的装置和方法，特别适用于交叉耦合的静态随机存取存储器（SRAM）单元中使用的那些。 根据本发明，SRAM单元的有源元件用于降低其晶体管栅极上的电压，而不影响电路的开关速度。 由于反相器输出的负载是固定的，所以优化了栅极电流的减小以最小化对存储器单元的开关波形的影响。 由具有不同费米电位的两种材料形成的有源元件用作整流结或二极管。 整流结还具有大的并联泄漏路径，当在该器件上施加相反极性的信号时，允许有限电流流动。

公开(公告)号：US07244986B2

公开(公告)日：2007-07-17

申请号：US10931901

申请日：2004-09-01

Applicant: Teiichiro Nishizaka

Inventor： Teiichiro Nishizaka

IPC: H01L29/792

CPC classification number: H01L27/11568 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/115 ,  H01L29/7923 ,  Y10S257/909

Abstract: A 2-bit cell is made up of first and second diffusion regions provided on a substrate surface, first and second storage nodes adjacent to the first and second diffusion region, first and second gate electrodes provided on first and second storage nodes, a third storage node provided on the substrate and a third gate electrode provided on the third storage node. The first and second gate electrodes are connected common to form word line electrodes. A control gate electrode at right angles to the word line electrodes and a third diffusion region in the substrate surface disposed at a longitudinal end of the control gate electrode are provided. A storage node, Node 1, of interest, with the control gate channel as a drain, is read without the intermediary of the second node, which is not of interest, such that reading of Node 1 unaffected by the second node.

Abstract translation: 2位单元由设置在基板表面上的第一和第二扩散区域，与第一和第二扩散区域相邻的第一和第二存储节点，设置在第一和第二存储节点上的第一和第二栅极电极，第三存储器 节点，设置在第三存储节点上的第三栅电极。 第一和第二栅极共同连接以形成字线电极。 提供了与字线电极成直角的控制栅极电极和设置在控制栅电极的纵向端的衬底表面中的第三扩散区域。 在不具有不感兴趣的第二节点的情况下读取感兴趣的具有控制门信道作为漏极的存储节点，节点1，使得节点1的读取不受第二节点的影响。

公开(公告)号：US20070052046A1

公开(公告)日：2007-03-08

申请号：US11210309

申请日：2005-08-24

Applicant: Stanley Chu ,  Sisira Gamage ,  Hyon-Jin Kwon

Inventor： Stanley Chu ,  Sisira Gamage ,  Hyon-Jin Kwon

IPC: H01L29/84

CPC classification number: G01L9/0054 ,  B81B2201/0264 ,  B81C3/001 ,  B81C2203/0109 ,  B81C2203/036 ,  G01L9/0042 ,  Y10S257/909 ,  Y10S438/909

Abstract: A pressure sensor includes a base substrate silicon fusion bonded to a cap substrate with a chamber disposed between the base substrate and the cap substrate. Each of the base substrate and the cap substrate include silicon. The base substrate includes walls defining a cavity and a diaphragm portion positioned over the cavity, wherein the cavity is open to an environment to be sensed. The chamber is hermetically sealed from the environment.

Abstract translation: 一种压力传感器包括：基底基底硅融合到盖基底上，其中腔室设置在基底基底和盖基片之间。 基底基板和盖基板中的每一个包括硅。 底部基底包括限定空腔的壁和位于空腔上方的隔膜部分，其中空腔对待感测的环境开放。 该室与环境密封。

公开(公告)号：US06995436B2

公开(公告)日：2006-02-07

申请号：US10860112

申请日：2004-06-04

Applicant: Toshiaki Kawasaki

Inventor： Toshiaki Kawasaki

IPC: H01L29/76

CPC classification number: G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11558 ,  Y10S257/909

Abstract: In a memory cell, the substrate contact region of an NMOS transistor and the well contact region of a PMOS transistor are arranged perpendicularly to a floating gate. In a cell array, the memory cell and another memory cell arranged axisymmetrically with respect to the memory cell are alternately arranged in the column direction to constitute a sub array, and the sub arrays arranged in the column direction are arranged in parallel or axisymmetically in the row direction. With this arrangement, the substrate contact region, the well contact region, and the diffusion region of the PMOS transistor can be shared between the adjacent memory cells, thereby reducing the area of the cell array.

Abstract translation: 在存储单元中，NMOS晶体管的衬底接触区域和PMOS晶体管的阱接触区域垂直于浮置栅极布置。 在单元阵列中，存储单元和相对于存储单元轴对称布置的另一个存储单元在列方向上交替布置以构成子阵列，并且沿列方向排列的子阵列平行或轴对称地布置在 行方向。 利用这种布置，可以在相邻的存储单元之间共享衬底接触区域，阱接触区域和PMOS晶体管的扩散区域，从而减小单元阵列的面积。

公开(公告)号：US06977209B2

公开(公告)日：2005-12-20

申请号：US10931905

申请日：2004-09-01

Applicant: Teiichiro Nishizaka

Inventor： Teiichiro Nishizaka

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/20 ,  H01L21/302

CPC classification number: H01L27/11568 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/115 ,  H01L29/7923 ,  Y10S257/909

Abstract: A 2-bit cell is made up of first and second diffusion regions provided on a substrate surface, first and second storage nodes adjacent to the first and second diffusion region, first and second gate electrodes provided on first and second storage nodes, a third storage node provided on the substrate and a third gate electrode provided on the third storage node. The first and second gate electrodes are connected common to form word line electrodes. A control gate electrode at right angles to the word line electrodes and a third diffusion region in the substrate surface disposed at a longitudinal end of the control gate electrode are provided. A storage node, Node 1, of interest, with the control gate channel as a drain, is read without the intermediary of the second node, which is not of interest, such that reading of Node1 unaffected by the second node.

Abstract translation: 2位单元由设置在基板表面上的第一和第二扩散区域，与第一和第二扩散区域相邻的第一和第二存储节点，设置在第一和第二存储节点上的第一和第二栅极电极，第三存储器 节点，设置在第三存储节点上的第三栅电极。 第一和第二栅极共同连接以形成字线电极。 提供了与字线电极成直角的控制栅极电极和设置在控制栅电极的纵向端的衬底表面中的第三扩散区域。 在不具有不感兴趣的第二节点的情况下读取感兴趣的具有控制门信道作为漏极的存储节点，节点1，使得节点1的读取不受第二节点的影响。

公开(公告)号：US20050042813A1

公开(公告)日：2005-02-24

申请号：US10931905

申请日：2004-09-01

Applicant: Teiichiro Nishizaka

Inventor： Teiichiro Nishizaka

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/00 ,  H01L21/8238

CPC classification number: H01L27/11568 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/115 ,  H01L29/7923 ,  Y10S257/909

Abstract: A 2-bit cell is made up of first and second diffusion regions provided on a substrate surface, first and second storage nodes adjacent to the first and second diffusion region, first and second gate electrodes provided on first and second storage nodes, a third storage node provided on the substrate and a third gate electrode provided on the third storage node. The first and second gate electrodes are connected common to form word line electrodes. A control gate electrode at right angles to the word line electrodes and a third diffusion region in the substrate surface disposed at a longitudinal end of the control gate electrode are provided. A storage node, Node 1, of interest, with the control gate channel as a drain, is read without the intermediary of the second node, which is not of interest, such that reading of Node 1 unaffected by the second node.

Abstract translation: 2位单元由设置在基板表面上的第一和第二扩散区域，与第一和第二扩散区域相邻的第一和第二存储节点，设置在第一和第二存储节点上的第一和第二栅极电极，第三存储器 节点，设置在第三存储节点上的第三栅电极。 第一和第二栅极共同连接以形成字线电极。 提供了与字线电极成直角的控制栅极电极和设置在控制栅电极的纵向端的衬底表面中的第三扩散区域。 在不具有不感兴趣的第二节点的情况下读取感兴趣的具有控制门信道作为漏极的存储节点，节点1，使得节点1的读取不受第二节点的影响。

公开(公告)号：US20050023564A1

公开(公告)日：2005-02-03

申请号：US10632007

申请日：2003-07-30

Applicant: Yi Ding

Inventor： Yi Ding

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  H01L27/10 ,  H01L29/76

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L27/105 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/7887 ,  H01L29/7923 ,  Y10S257/905 ,  Y10S257/909 ,  Y10S257/92

Abstract: In a nonvolatile memory array in which each cell (110) has two floating gates (160), for any two consecutive memory cells, one source/drain region (174) of one of the cells and one source/drain region of the other one of the cells are provided by a contiguous region of the appropriate conductivity type (e.g. N type) formed in a semiconductor substrate (120). Each such contiguous region provides source/drain regions to only two of the memory cells in that column. The bitlines (180) overlie the semiconductor substrate in which the source/drain regions are formed. The bitlines are connected to the source/drain regions.

Abstract translation: 在其中每个单元（110）具有两个浮动栅极（160）的非易失性存储器阵列中，对于任何两个连续的存储单元，一个单元的一个源极/漏极区域（174）和另一个单元的一个源极/漏极区域 的单元由形成在半导体衬底（120）中的适当导电类型（例如N型）的连续区域提供。 每个这样的连续区域仅向该列中的两个存储单元提供源极/漏极区域。 位线（180）覆盖其中形成源极/漏极区域的半导体衬底。 位线连接到源极/漏极区域。

公开(公告)号：US06809373B2

公开(公告)日：2004-10-26

申请号：US10632368

申请日：2003-08-01

Applicant: Teiichiro Nishizaka

Inventor： Teiichiro Nishizaka

IPC: H01L29788

CPC classification number: H01L27/11568 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/115 ,  H01L29/7923 ,  Y10S257/909

Abstract: A 2-bit cell is made up by first and second diffusion regions provided in a substrate surface in separation from each other, first and second dielectric films provided on the substrate adjacent to the first and second diffusion region, first and second gate electrodes provided on first and second dielectric films, a third insulating film provided on the substrate and a third gate electrode provided on the third insulating film. The first and second gate electrodes are connected common to form word line electrodes. A control gate electrode extending in a direction at right angles to the word line electrodes and a third diffusion region in the substrate surface disposed at a longitudinal end of the control gate electrode are provided. In reading a storage node Node1 of interest, read operation is performed with the control gate channel as a drain, such that the storage node Node1 of interest is read without the intermediary of the node Node2 which is not of interest, with the consequence that read of the node Node1 is not affected by the node Node2 which is not of interest.

Abstract translation: 2位电池由设置在基板表面中的彼此分离的第一和第二扩散区域构成，设置在与第一和第二扩散区域相邻的基板上的第一和第二电介质膜，设置在第一和第二扩散区上的第一和第二栅极电极 第一和第二介电膜，设置在基板上的第三绝缘膜和设置在第三绝缘膜上的第三栅电极。 第一和第二栅极共同连接以形成字线电极。 设置在与字线电极成直角的方向上延伸的控制栅极电极和设置在控制栅电极的纵向端的衬底表面中的第三扩散区域。 在读取感兴趣的存储节点Node1时，以控制门信道为漏极执行读操作，使得感兴趣的存储节点Node1被读取而不需要不感兴趣的节点Node2，因此读取 节点Node1不受不感兴趣的节点Node2的影响。