公开(公告)号：US20080105929A1

公开(公告)日：2008-05-08

申请号：US11902391

申请日：2007-09-21

Applicant: Masatomo Eimitsu ,  Takanori Saeki

Inventor： Masatomo Eimitsu ,  Takanori Saeki

IPC: H01L27/088

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  Y10S257/909 ,  Y10S257/919

Abstract: According to an aspect of the present invention, there is provided a semiconductor IC that includes a plurality of standard cells arranged in a first direction on a semiconductor substrate, and a first diffusion layer connected to a first power source and a second diffusion layer connected to a second power source in the each standard cell, wherein the first diffusion layers as well as the second diffusion layers of neighboring standard cells are integrally formed.

Abstract translation: 根据本发明的一个方面，提供了一种半导体IC，其包括在半导体衬底上沿第一方向布置的多个标准单元，以及连接到第一电源的第一扩散层和连接到 在每个标准单元中的第二电源，其中相邻标准单元的第一扩散层以及第二扩散层是一体形成的。

公开(公告)号：US07042007B2

公开(公告)日：2006-05-09

申请号：US10824426

申请日：2004-04-15

Applicant: Takatoshi Yasui ,  Atsuhiro Kajiya

Inventor： Takatoshi Yasui ,  Atsuhiro Kajiya

IPC: H01L23/58

CPC classification number: H01L22/34 ,  H01L27/088 ,  H01L2924/0002 ,  Y10S257/919 ,  H01L2924/00

Abstract: A single evaluation portion is formed by disposing a plurality of MIS transistors used for evaluation having substantially the same structure as that of an actually used MIS transistor. In the evaluation portion, the respective source regions, drain regions, and gate electrodes of the MIS transistors used for evaluation are electrically connected in common to a source pad, a drain pad, and a gate pad, respectively. If the effective gate width of the single evaluation portion exceeds a given value, variations in characteristics evaluated by the evaluation portion approach variations in the characteristics of the entire semiconductor device. The accuracy of evaluating the characteristics of the semiconductor device can thus be improved by using the evaluation portion.

Abstract translation: 单个评估部分通过设置用于评估的多个MIS晶体管形成，其具有与实际使用的MIS晶体管基本相同的结构。 在评估部分中，用于评估的MIS晶体管的各个源极区域，漏极区域和栅极电极分别电连接到源极焊盘，漏极焊盘和栅极焊盘。 如果单个评估部分的有效栅极宽度超过给定值，则由评估部分评估的特性的变化导致整个半导体器件的特性的变化。 因此，可以通过使用评价部来提高评价半导体装置的特性的精度。

公开(公告)号：US20040084671A1

公开(公告)日：2004-05-06

申请号：US10288193

申请日：2002-11-05

Applicant: Chartered Semiconductor Manufacturing Ltd.

Inventor： Zhigang Song ,  Shailesh Redkar ,  Chong Khiam Oh

IPC: H01L021/00 ,  G01R031/26 ,  H01L023/58

CPC classification number: H01L22/34 ,  G01R31/311 ,  Y10S257/911 ,  Y10S257/919

Abstract: A new test structure to locate bridging defects in a conductive layer of an integrated circuit device is achieved. The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles comprises the conductive layer. The rectangles are not connected to the line or to other rectangles. Near edges of the rectangles and of the line are parallel. The rectangles are floating. The test structure is used with a passive voltage contrast test in a scanning electron microscope. A test structure and method to measure critical dimensions is disclosed.

Abstract translation: 实现了在集成电路器件的导电层中定位桥接缺陷的新的测试结构。 测试结构包括包括覆盖在衬底上的导电层的线。 线连接到地面。 多个矩形包括导电层。 矩形不连接到线或其他矩形。 矩形和线的近边是平行的。 矩形是浮动的。 测试结构与扫描电子显微镜中的被动电压对比度测试一起使用。 公开了一种测量关键尺寸的测试结构和方法。

公开(公告)号：US5644159A

公开(公告)日：1997-07-01

申请号：US613939

申请日：1996-03-13

Applicant: Masao Arimoto

Inventor： Masao Arimoto

IPC: H01L27/04 ,  G05F3/30 ,  H01L21/822 ,  H01L27/06 ,  H01L27/082 ,  H01L27/10

CPC classification number: H01L27/0623 ,  G05F3/30 ,  H01L27/082 ,  Y10S257/919

Abstract: A semiconductor device implemented using a transistor (Q1) including at least one emitter (E1) and a transistor (Q2) which is larger than the transistor (Q1) including n emitters (E21 to E2n) each having the same area as the emitter (E1) of the transistor (Q1). The emitter (E1) of the transistor (Q1) is disposed between the emitters (E21 to E2n) of the transistor (Q2). When there is deflection of a substrate due to a stress to cause distortion in shape of the emitters, the emitter (E1) has much less distortion in shape than the emitters located on the end portions of the row region in the longitudinal direction. Since the transistor (Q2) has a number of emitters, the distortion in shape of the emitters (E21 to E2n) of the transistor (Q2), if any, has little effect on the whole.

Abstract translation: 一种使用包括至少一个发射极（E1）和晶体管（Q2）的晶体管（Q1）的半导体器件，该晶体管（Q1）和晶体管（Q1）大于包括与发射极相同的面积的n个发射极（E21〜E2n） E1）。 晶体管（Q1）的发射极（E1）配置在晶体管（Q2）的发射极（E21〜E2n）之间。 当由于应力引起的基板由于发射体的形状发生变形而发生偏转时，发射极（E1）的形状畸变比位于行区域的纵向方向的端部上的发射体的形状小得多。 由于晶体管（Q2）具有多个发射极，因此晶体管（Q2）的发射极（E21〜E2n）的形状变形（总之）几乎没有影响。

公开(公告)号：US5298762A

公开(公告)日：1994-03-29

申请号：US982009

申请日：1992-09-28

Applicant: Szutsun S. Ou

Inventor： Szutsun S. Ou

IPC: H01L29/06 ,  H01L29/74 ,  H01S5/00 ,  H01S5/32 ,  H01S5/34 ,  H01S5/343 ,  H01L27/14

CPC classification number: B82Y20/00 ,  H01L31/035236 ,  H01L31/105 ,  H01S5/06203 ,  H01S5/34 ,  H01S5/305 ,  H01S5/3054 ,  H01S5/3095 ,  H01S5/3211 ,  H01S5/3432 ,  Y10S257/919

Abstract: A semiconductor-insulator-semiconductor (SIS) structure diode device for providing fast optoelectronic switching with stimulated emission. The device includes a substrate which has a buffer layer disposed on top thereof. An n-type cladding layer is disposed on top of the buffer layer. An undoped i-region is disposed on top of the buffer layer. The i-region includes at least one quantum well disposed between two waveguide layers. A lightly doped p-type cladding layer is disposed on top of the i-region. A contact layer is further disposed on top of the p-type cladding layer. First and second contact terminals are included for providing a two-terminal device. The diode advantageously provides good lasing performance, significant negative differential resistance and strong light sensitivity. In an alternate embodiment, a third terminal is connected to the undoped i-region to thereby form a three terminal device.

Abstract translation: 半导体 - 绝缘体半导体（SIS）结构二极管器件，用于提供具有受激发射的快速光电开关。 该装置包括具有设置在其顶部上的缓冲层的基板。 n型包层设置在缓冲层的顶部。 未掺杂的i区域设置在缓冲层的顶部。 i区域包括设置在两个波导层之间的至少一个量子阱。 轻掺杂的p型覆层设置在i区的顶部。 接触层还设置在p型覆层的顶部。 包括第一和第二接触端子用于提供两端装置。 二极管有利地提供良好的激光性能，显着的负差分电阻和强光敏感性。 在替代实施例中，第三端子连接到未掺杂的i区域，从而形成三端子器件。

公开(公告)号：US3972113A

公开(公告)日：1976-08-03

申请号：US467563

申请日：1974-05-06

Applicant: Josuke Nakata ,  Takeshi Yamamoto ,  Hitoshi Matufuzi

Inventor： Josuke Nakata ,  Takeshi Yamamoto ,  Hitoshi Matufuzi

IPC: H01L21/033 ,  H01L21/223 ,  H01L21/78 ,  B01J17/00

CPC classification number: H01L21/033 ,  H01L21/223 ,  H01L21/78 ,  Y10S148/028 ,  Y10S148/051 ,  Y10S148/106 ,  Y10S148/145 ,  Y10S148/151 ,  Y10S257/919 ,  Y10S438/965

Abstract: Boron is diffused into selected areas of each main face of an N silicon substrate and gallium is diffused into the entire main face to form a P-N junction including deeper portions alternating shallower portion. Selective etching is effected to form grooves in the shallower junction portions for dividing the P-N junction. Both main faces of the substrate except for the grooves are metallized and a passivation layer is applied to each groove. Alternatively, in order to form the P-N junction as above described, gallium is selectively diffused in the substrate followed by a further diffusion of the gallium.

Abstract translation: 硼被扩散到N硅衬底的每个主面的选定区域中，并且镓扩散到整个主面中以形成包括较浅部分交替较浅部分的P-N结。 进行选择性蚀刻以在较浅的接合部分中形成用于划分P-N结的凹槽。 除了凹槽之外的基板的两个主面被金属化，并且钝化层被施加到每个凹槽。 或者，为了形成如上所述的P-N结，镓选择性地​​扩散到衬底中，随后进一步扩散镓。

公开(公告)号：US20040212016A1

公开(公告)日：2004-10-28

申请号：US10824426

申请日：2004-04-15

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD

Inventor： Takatoshi Yasui ,  Atsuhiro Kajiya

IPC: H01L029/76

CPC classification number: H01L22/34 ,  H01L27/088 ,  H01L2924/0002 ,  Y10S257/919 ,  H01L2924/00

Abstract: A single evaluation portion is formed by disposing a plurality of MIS transistors used for evaluation having substantially the same structure as that of an actually used MIS transistor. In the evaluation portion, the respective source regions, drain regions, and gate electrodes of the MIS transistors used for evaluation are electrically connected in common to a source pad, a drain pad, and a gate pad, respectively. If the effective gate width of the single evaluation portion exceeds a given value, variations in characteristics evaluated by the evaluation portion approach variations in the characteristics of the entire semiconductor device. The accuracy of evaluating the characteristics of the semiconductor device can thus be improved by using the evaluation portion.

Abstract translation: 单个评估部分通过设置用于评估的多个MIS晶体管形成，其具有与实际使用的MIS晶体管基本相同的结构。 在评估部分中，用于评估的MIS晶体管的各个源极区域，漏极区域和栅极电极分别电连接到源极焊盘，漏极焊盘和栅极焊盘。 如果单个评估部分的有效栅极宽度超过给定值，则由评估部分评估的特性的变化导致整个半导体器件的特性的变化。 因此，可以通过使用评价部来提高评价半导体装置的特性的精度。

公开(公告)号：US20040080362A1

公开(公告)日：2004-04-29

申请号：US10689128

申请日：2003-10-20

Inventor： Siva G. Narendra ,  Stephen H. Tang ,  Zachary Keer ,  Vivek K. De

IPC: G05F003/02

CPC classification number: G05F3/245 ,  Y10S257/919

Abstract: A current reference, which may be fabricated independently, on a die, as part of an integrated circuit, or a system, or in various other forms, is disclosed. The current reference may include a voltage source having a substantially temperature stable output voltage, a first semiconductor device biased by the substantially temperature stable output voltage to provide a first output current, and a second semiconductor device providing a second output current, wherein a reference current is provided approximately equal to the difference between the first and second output currents.

Abstract translation: 公开了可以在芯片上作为集成电路或系统的一部分或以各种其它形式单独制造的电流基准。 电流参考可以包括具有基本上温度稳定的输出电压的电压源，由基本上温度稳定的输出电压偏置以提供第一输出电流的第一半导体器件，以及提供第二输出电流的第二半导体器件，其中参考电流 被提供大致等于第一和第二输出电流之间的差。

公开(公告)号：US06590448B1

公开(公告)日：2003-07-08

申请号：US09654434

申请日：2000-09-01

Applicant: Rodney T. Burt

Inventor： Rodney T. Burt

IPC: H03F328

CPC classification number: H03F3/68 ,  H03F3/45071 ,  H04R2225/59 ,  Y10S257/919

Abstract: A technique is disclosed which facilitates the layout of op amp cells, for example, two-stage op amp cells or three-stage op amp cells, to provide larger operational amplifiers. In accordance with one aspect, the op amp cells can be suitably coupled in parallel to provide a larger operational amplifier. This paralleling aspect can be facilitated by connecting the respective negative and positive inputs of a predetermined number of input gm stages together, connecting the outputs of a predetermined number of output gm stages together, and connecting a predetermined number of intermediate internal nodes between the input gm stages and the output gm stages together, without the occurrence of saturation of the internal nodes. In addition, the input and output characteristics of operational amplifier can be suitably improved. Further, the plurality of op amp cells can be selectively configurable to be connected in parallel with other op amp cells through the use of, for example, manual switches or other suitable electrical contacts, jumpers and the like, or programmable switches. Moreover, the op amp cells can be suitably configured in various arrangements, such as a two-stage cell having a first gm stage with a single-ended output, a two-stage cell having a first gm stage with a differential output, or a three-stage op amp cell. As a result, the method of the present invention can provide a substantial advantage in the design of integrated circuits in which the development costs are high, and multiple custom mask sets are too expensive to be practical.

Abstract translation: 公开了一种有利于运算放大器的布局的技术，例如两级运算放大器或三级运算放大器，以提供更大的运算放大器。 根据一个方面，运算放大器电池可以适当地并联耦合以提供更大的运算放大器。 通过将预定数量的输入gm级的相应负和正输入连接在一起，将预定数量的输出gm级的输出连接在一起，并将预定数量的中间内部节点连接在输入gm之间，可以促进并行方面 阶段和输出gm阶段，而不会发生内部节点的饱和。 此外，可以适当地提高运算放大器的输入和输出特性。 此外，可以通过使用例如手动开关或其它合适的电触点，跳线等或可编程开关来选择性地配置多个运算放大器单元与其它运算放大器并联连接。 此外，可以以各种布置适当地配置运算放大器单元，例如具有单端输出的第一gm级的两级单元，具有差分输出的第一gm级的两级单元，或者 三级运算放大器。 结果，本发明的方法可以在开发成本高的集成电路的设计中提供显着的优点，并且多个定制掩模组太贵而不实际。

公开(公告)号：US20030111698A1

公开(公告)日：2003-06-19

申请号：US10025047

申请日：2001-12-19

Applicant: Intel Corporation

Inventor： Siva G. Narendra ,  Stephen H. Tang ,  Zachary Keer ,  Vivek K. De

IPC: G11C011/00 ,  H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113 ,  H01L031/119

CPC classification number: G05F3/245 ,  Y10S257/919

Abstract: A current reference, which may be fabricated on a die, as part of an integrated circuit, or in various other forms, is disclosed. The current reference includes two current sources, both of which provide a substantially temperature stable output current, which may use a differencing circuit to provide a reference output current having a magnitude approximately equal to the difference between the magnitudes of the two substantially temperature stable output currents.

Abstract translation: 公开了可以在芯片上制造的作为集成电路的一部分或以各种其它形式的电流参考。 电流参考文献包括两个电流源，它们都提供基本上温度稳定的输出电流，其可以使用差分电路来提供参考输出电流，该参考输出电流的幅度近似等于两个基本上温度稳定的输出电流的幅度之差 。