公开(公告)号：US20040212016A1

公开(公告)日：2004-10-28

申请号：US10824426

申请日：2004-04-15

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD

Inventor： Takatoshi Yasui ,  Atsuhiro Kajiya

IPC: H01L029/76

CPC classification number: H01L22/34 ,  H01L27/088 ,  H01L2924/0002 ,  Y10S257/919 ,  H01L2924/00

Abstract: A single evaluation portion is formed by disposing a plurality of MIS transistors used for evaluation having substantially the same structure as that of an actually used MIS transistor. In the evaluation portion, the respective source regions, drain regions, and gate electrodes of the MIS transistors used for evaluation are electrically connected in common to a source pad, a drain pad, and a gate pad, respectively. If the effective gate width of the single evaluation portion exceeds a given value, variations in characteristics evaluated by the evaluation portion approach variations in the characteristics of the entire semiconductor device. The accuracy of evaluating the characteristics of the semiconductor device can thus be improved by using the evaluation portion.

Abstract translation: 单个评估部分通过设置用于评估的多个MIS晶体管形成，其具有与实际使用的MIS晶体管基本相同的结构。 在评估部分中，用于评估的MIS晶体管的各个源极区域，漏极区域和栅极电极分别电连接到源极焊盘，漏极焊盘和栅极焊盘。 如果单个评估部分的有效栅极宽度超过给定值，则由评估部分评估的特性的变化导致整个半导体器件的特性的变化。 因此，可以通过使用评价部来提高评价半导体装置的特性的精度。