公开(公告)号：US20040266090A1

公开(公告)日：2004-12-30

申请号：US10494620

申请日：2004-05-04

发明人： Mitsuhiro Nakamura

IPC分类号： H01L021/8238 ,  H01L021/336 ,  H01L031/119 ,  H01L031/113 ,  H01L029/76 ,  H01L021/38 ,  H01L021/22

CPC分类号： H01L29/802 ,  H01L21/2258 ,  H01L29/66924

摘要： To provide a semiconductor device able to be made uniform in diffusion depth of the impurity in a diffusion layer by a single diffusion and to give the desired threshold voltage and improved in yield and a method of producing the same. The device has a channel layer 16 formed on a substrate 12, a diffusion stop layer 17 formed on the top surface of the channel layer 16, a diffusion layer 18 formed on the top surface of the diffusion stop layer, and a doping region 25 formed adjoining the diffusion stop layer 17 at least at part of the diffusion layer 18 and having an impurity diffused in it, the diffusion stop layer 17 having a slower diffusion rate of the impurity than the diffusion rate of the diffusion layer 18 and stopping diffusion of the impurity from the diffusion layer 18.

摘要翻译： 提供能够通过单个扩散使扩散层中的杂质的扩散深度均匀的半导体器件，并提供所需的阈值电压并提高其产率及其制造方法。 该器件具有形成在衬底12上的沟道层16，形成在沟道层16的顶表面上的扩散阻挡层17，形成在扩散阻挡层的顶表面上的扩散层18和形成的掺杂区25 至少在扩散层18的一部分附近扩散阻挡层17，并且在其中扩散杂质，扩散阻挡层17具有比扩散层18的扩散速率更慢的杂质扩散速率，并阻止扩散层17的扩散。 来自扩散层18的杂质。

公开(公告)号：US20040262698A1

公开(公告)日：2004-12-30

申请号：US10604077

申请日：2003-06-25

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Edward J. Nowak

IPC分类号： H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L021/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： The invention provides a method of manufacturing a fin-type field effect transistor (FinFET) that forms a unique FinFET that has a first fin with a central channel region and source and drain regions adjacent the channel region, a gate intersecting the first fin and covering the channel region, and a second fin having only a channel region.

摘要翻译： 本发明提供一种制造翅片型场效应晶体管（FinFET）的方法，其形成独特的FinFET，其具有第一鳍片，中心沟道区域和与沟道区域相邻的源极和漏极区域，与第一鳍片相交的栅极和覆盖层 沟道区域和仅具有沟道区域的第二鳍片。

公开(公告)号：US20040262697A1

公开(公告)日：2004-12-30

申请号：US10854772

申请日：2004-05-27

申请人： INFINEON TECHNOLOGIES

发明人： Gerhard Enders ,  Helmut Schneider ,  Peter Voigt

IPC分类号： H01L029/76

CPC分类号： H01L29/66583 ,  H01L21/28247 ,  H01L29/66553 ,  H01L29/6656

摘要： A method for fabricating a semiconductor gate structure including depositing at least one sacrificial layer on a semiconductor substrate; patterning the at least one sacrificial layer to form at least one cutout in the at least one sacrificial layer for uncovering the semiconductor substrate; forming a sidewall spacer over the sidewalls of the at least one sacrificial layer in the at least one cutout; forming a gate dielectric on the semiconductor substrate in the cutout; providing a gate electrode in the at least one cutout in the at lest one sacrificial layer; and removing the at least one sacrificial layer for the uncovering the gate electrode surrounded by the sidewall spacer. A semiconductor device is also provided.

摘要翻译： 一种用于制造半导体栅极结构的方法，包括在半导体衬底上沉积至少一个牺牲层; 图案化所述至少一个牺牲层以在所述至少一个牺牲层中形成至少一个切口以露出所述半导体衬底; 在所述至少一个切口中的所述至少一个牺牲层的侧壁上形成侧壁间隔物; 在所述切口中的所述半导体基板上形成栅极电介质; 在所述至少一个牺牲层中的所述至少一个切口中提供栅电极; 以及去除所述至少一个牺牲层以露出由所述侧壁间隔物包围的所述栅电极。 还提供了半导体器件。

公开(公告)号：US20040262683A1

公开(公告)日：2004-12-30

申请号：US10608870

申请日：2003-06-27

发明人： Mark T. Bohr ,  Tahir Ghani ,  Stephen Cea ,  Kaizad Mistry ,  Christopher P. Auth ,  Mark Armstrong ,  Keith E. Zawadzki

IPC分类号： H01L029/76

CPC分类号： H01L29/66628 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848

摘要： Optimal strain in the channel region of a PMOS transistor is provided by silicon alloy material in the junction regions of the device in a non-planar relationship with the surface of the substrate. The silicon alloy material, the dimensions of the silicon alloy material, as well as the non-planar relationship of the silicon alloy material with the surface of the substrate are selected so that the difference between the lattice spacing of the silicon alloy material and of the substrate causes strains in the silicon alloy material below the substrate surface, as well as above the substrate surface, to affect an optimal silicon alloy induced strain in the substrate channel. In addition, the non-planar relationship may be selected so that any strains caused by different lattice spaced layers formed over the silicon alloy material have a reduced effect on the strain in the channel region.

摘要翻译： PMOS晶体管的沟道区域中的最佳应变由硅合金材料在与衬底表面非平面关系的器件的接合区域中提供。 选择硅合金材料，硅合金材料的尺寸以及硅合金材料与基板表面的非平面关系，使得硅合金材料的晶格间距与 衬底在衬底表面以下以及衬底表面之上的硅合金材料中引起应变，以影响衬底通道中最佳的硅合金诱导应变。 此外，可以选择非平面关系，使得由在硅合金材料上形成的不同格子间隔层引起的任何应变对通道区域中的应变具有降低的影响。

公开(公告)号：US20040262676A1

公开(公告)日：2004-12-30

申请号：US10871742

申请日：2004-06-18

发明人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

IPC分类号： H01L029/76

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： Methods for fabricating Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is formed on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is formed in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is formed on the first insulation layer and a second insulation layer is formed on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin. Related Fin-FETs are also provided.

摘要翻译： 提供制造鳍场效应晶体管（Fin-FET）的方法。 翅片形成在集成电路基板上。 翅片限定集成电路基板上的沟槽。 第一绝缘层形成在沟槽中，使得第一绝缘层的表面在鳍片的暴露在翅片的侧壁的表面下方凹进。 保护层形成在第一绝缘层上，并且第二绝缘层形成在沟槽中的保护层上，使得保护层位于第二绝缘层和鳍的侧壁之间。 还提供了相关的Fin-FET。

公开(公告)号：US20040262671A1

公开(公告)日：2004-12-30

申请号：US10848923

申请日：2004-05-19

申请人： Micron Technology, Inc.

发明人： Ebrahim Abedifard

IPC分类号： H01L029/76 ,  H01L031/062

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： Floating-gate memory cells having a trench source-line contact are suited for increased packing densities without a need for low-resistance ground straps placed at regular intervals across a memory array. Such floating-gate memory cells have their drain regions and source regions formed in a first semiconductor region having a first conductivity type. This first semiconductor region is separated from the underlying substrate by an interposing second semiconductor region having a second conductivity type different from the first conductivity type. The source regions of the memory cells are coupled to the second semiconductor region as a common source line. Such memory cells can be programmed, read and erased by applying various potential levels to their control gates, their drain regions, the first semiconductor region, and the second semiconductor region.

公开(公告)号：US20040256691A1

公开(公告)日：2004-12-23

申请号：US10822643

申请日：2004-04-12

发明人： Michio Nemoto ,  Manabu Takei ,  Tatsuya Naito

IPC分类号： H01L021/8238 ,  H01L029/76

CPC分类号： H01L29/0646 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0834 ,  H01L29/404 ,  H01L29/7395

摘要： A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a nnull drift layer, the MOS gate structure including a pnull base layer formed in a front surface region of the drift layer, an nnull emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure. A pnull isolation region surrounds the MOS gate structure through the drift layer and extends across whole thickness of the drift layer. A pnull collector layer is formed on a rear surface of the drift layer and connects to a rear side of the isolation region. A distance W is greater than a thickness d, in which the distance W is a distance from an outermost position of a portion of the emitter electrode, the portion being in contact with the base layer, to an innermost position of the isolation region, and the thickness d is a dimension in a depth direction of the drift layer.

摘要翻译： 没有显示隔离区域对反向恢复峰值电流的不利影响的反向阻挡半导体器件，其具有显示令人满意的软恢复的击穿耐受结构，其抑制基本上伴随常规反向阻断IGBT的反向漏电流的恶化，并且 公开了令人满意的低导通电压。 该器件包括形成在n漂移层上的MOS栅极结构，该MOS栅极结构包括形成在该漂移层的前表面区域中的p +基极层，形成在该基极层的表面区域中的n +发射极区域， 覆盖发射极区域和漂移层之间的基底层的表面区域的栅极绝缘膜，以及形成在栅极绝缘膜上的栅电极。 发射极电极与MOS栅极结构的发射极区域和基极层接触。 p +隔离区域通过漂移层包围MOS栅极结构，并延伸穿过漂移层的整个厚度。 p +集电极层形成在漂移层的后表面上并连接到隔离区的后侧。 距离W大于厚度d，其中距离W是距离发射电极的一部分的最外侧位置（与基层接触的部分）到隔离区域的最内位置的距离，以及 厚度d是漂移层的深度方向的尺寸。

公开(公告)号：US20040256669A1

公开(公告)日：2004-12-23

申请号：US10888776

申请日：2004-07-09

发明人： Philip L. Hower ,  John Lin ,  Sameer P. Pendharkar ,  Steven L. Merchant

IPC分类号： H01L029/76

CPC分类号： H01L29/7816 ,  H01L23/4824 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Segmented power transistors and fabrication methods are disclosed in which transistor segments are spaced from one another to facilitate thermal diffusion, and in which other electrical devices can be formed in the spaces between transistor segments.

摘要翻译： 公开了分段功率晶体管和制造方法，其中晶体管段彼此间隔开以促进热扩散，并且其中可以在晶体管段之间的空间中形成其它电气器件。

公开(公告)号：US20040256651A1

公开(公告)日：2004-12-23

申请号：US10896547

申请日：2004-07-22

申请人： Infineon Technologies AG ,  International Business Machines Corporation

发明人： Thomas W. Dyer ,  Andreas Knorr ,  Laertis Economikos ,  Scott Halle ,  Rajeev Malik ,  Norbert Arnold

IPC分类号： H01L029/76 ,  H01L021/8242 ,  H01L031/119 ,  H01L029/94 ,  H01L021/336

CPC分类号： H01L27/10864 ,  H01L27/10891

摘要： A Top Oxide Method is used to form an oxide layer over an array of vertical transistors as in a trench dynamic random access memory (DRAM) array with vertically stacked access metal oxide semiconductor field effect transistors (MOSFETs). The Top Oxide is formed by first forming the vertical devices with the pad nitride remaining in place. Once the devices have been formed and the gate polysilicon has been planarized down to the surface of the pad nitride, the pad nitride is stripped away leaving the tops of the gate polysilicon plugs extending above the active silicon surface. This pattern of polysilicon plugs defines the pattern over which the Top Oxide is deposited. The deposited Top Oxide fills the regions between and on top of the polysilicon plugs. The Top Oxide is then planarized back to the tops of the polysilicon plugs so contacts can be made between the passing interconnects and the gates of the vertical devices. The Top Oxide layer serves to separate the passing interconnects from the active silicon thereby reducing capacitive coupling between the two levels and providing a robust etch-stop layer for the reactive ion etch (RIE) patterning of the subsequent interconnect level.

摘要翻译： 如在具有垂直堆叠的存取金属氧化物半导体场效应晶体管（MOSFET）的沟槽动态随机存取存储器（DRAM）阵列中，顶部氧化物方法用于在垂直晶体管阵列上形成氧化物层。 顶部氧化物通过首先形成垂直装置而形成，其中衬垫氮化物保持就位。 一旦器件已经形成并且栅极多晶硅已经被平坦化到衬底氮化物的表面之下，衬垫氮化物被剥离掉，留下栅极多晶硅插塞的顶部延伸到活性硅表面之上。 这种多晶硅插塞的图形定义了顶部氧化物沉积的图案。 沉积的顶部氧化物填充多晶硅插塞之间和之上的区域。 然后将顶部氧化物平面化回多晶硅插塞的顶部，因此可以在通过的互连件和垂直装置的栅极之间形成接触。 顶部氧化物层用于将通过的互连与有源硅分离，从而减少两个电平之间的电容耦合，并提供用于后续互连电平的反应离子蚀刻（RIE）图案化的鲁棒蚀刻停止层。

公开(公告)号：US20040256644A1

公开(公告)日：2004-12-23

申请号：US10495653

申请日：2004-08-18

发明人： Thomas Kugler ,  Magnus Berggren ,  Tommi Remonen ,  Anna Ingalill Malmstrom ,  Bjorn Knuthammar ,  Petronella Norberg

IPC分类号： H01L029/76

CPC分类号： H01L51/0508 ,  G06K19/027 ,  H01L51/0037 ,  H01L51/0512 ,  H01Q1/22 ,  H01Q1/2225

摘要： An electrochemical device is provided, comprising a source contact connected to a first antenna pad, a drain contact connected to a second antenna pad, at least one gate electrode, an electrochemically active element arranged between, and in direct electrical contact with, the source and drain contacts, which electrochemically active element comprises a transistor channel and is of a material comprising an organic material having the ability of electrochemically altering its conductivity through change of redox state thereof, and a solidified electrolyte in direct electrical contact with the electrochemically active element and the at least one gate electrode and interposed between them in such a way that electron flow between the electrochemically active element and the gate electrode(s) is prevented. In the device, flow of electrons between source contact and drain contact is controllable by means of a voltage applied to the gate electrode(s).

摘要翻译： 提供了一种电化学装置，其包括连接到第一天线焊盘的源极触点，连接到第二天线焊盘的漏极触点，至少一个栅极电极，布置在源极和与源极直接电接触的电化学活性元件;以及 漏极触点，其电化学活性元件包括晶体管沟道，并且是包括具有通过其氧化还原状态的电化学改变其导电性的能力的有机材料的材料，以及与电化学活性元件直接电接触的固化电解质， 至少一个栅电极并且插入在它们之间，使得电化学活性元件和栅电极之间的电子流被阻止。 在器件中，源极接触和漏极接触之间的电子流可以通过施加到栅电极的电压来控制。